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xilinx xc9572 cpld 实现的伺服电机控制器

  signal NlwInverterSignal_CLR0_D2_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_CLR0_D2_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_CLR0_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_CLR0_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CLR0_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_CLR0_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_CLR0_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_CLR0_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_CLR0_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_CLR0_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_CLR0_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CLR0_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CLR1_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CLR1_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_CLR1_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_CLR1_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_CLR1_D2_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_CLR1_D2_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_CLR1_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_CLR1_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CLR1_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_CLR1_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_CLR1_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_CLR1_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_CLR1_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_CLR1_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_CLR1_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CLR1_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CSA2_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CSA2_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_CSA2_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_CSA2_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_CSA2_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_CSA2_D2_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_CSA2_D2_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_CSA2_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_CSA2_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CSA2_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_CSA2_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_CSA2_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_CSA2_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_CSA2_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_CSA2_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_CSA2_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_CSA2_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CSA2_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q41_2_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q41_2_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q41_2_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q41_2_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q41_2_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q41_2_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q4_2_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q4_2_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q4_2_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q4_2_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q4_2_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q4_2_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CSA1_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CSA1_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_CSA1_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_CSA1_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_CSA1_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_CSA1_D2_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_CSA1_D2_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_CSA1_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_CSA1_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CSA1_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_CSA1_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_CSA1_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_CSA1_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_CSA1_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_CSA1_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_CSA1_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_CSA1_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CSA1_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q41_3_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q41_3_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q41_3_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q41_3_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q41_3_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q4_3_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q4_3_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q4_3_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q4_3_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q4_3_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CS_U_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CS_U_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CS_U_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_CS_U_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_CS_U_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_CS_U_D2_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_CS_U_D2_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_CS_U_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_CS_U_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CS_U_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CS_U_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_CS_U_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_CS_U_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_CS_U_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_CS_U_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_CS_U_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_CS_U_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CS_U_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_ALMR_OBUF_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_ALMR_OBUF_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_ALMR_OBUF_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_ALMR_OBUF_D2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_0_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_0_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_0_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_0_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_1_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_1_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_1_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_1_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_2_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_2_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_2_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_2_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_3_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_3_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_3_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_3_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_4_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_4_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_4_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_4_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_5_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_5_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_5_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_5_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_6_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_6_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_6_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_6_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_7_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_7_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_7_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXN_8_7_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_UART0_OBUF_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_UART0_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_UART0_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_UART0_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_UART0_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_UART0_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_UART0_OBUF_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_UART0_OBUF_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q41_2_XLXI_57_Q41_2_CLKF_INT_D2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q4_2_XLXI_57_Q4_2_CLKF_INT_D2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_6_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_7_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_8_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_9_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_10_TRST_IN0 : STD_LOGIC; 
  signal XLXI_57_Q4 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
begin
  N3927_21 : X_BUF
    port map (
      I => D(1),
      O => N3927
    );
  N3925_22 : X_BUF
    port map (
      I => D(0),
      O => N3925
    );
  CS_IBUF_23 : X_BUF
    port map (
      I => CS,
      O => CS_IBUF
    );
  A2_IBUF_24 : X_BUF
    port map (
      I => A2,
      O => A2_IBUF
    );
  A1_IBUF_25 : X_BUF
    port map (
      I => A1,
      O => A1_IBUF
    );
  A0_IBUF_26 : X_BUF
    port map (
      I => A0,
      O => A0_IBUF
    );
  WR_IBUF_27 : X_BUF
    port map (
      I => WR,
      O => WR_IBUF
    );
  RESET_IBUF_28 : X_BUF
    port map (
      I => RESET,
      O => RESET_IBUF
    );
  N3937_29 : X_BUF
    port map (
      I => D(7),
      O => N3937
    );
  N3929_30 : X_BUF
    port map (
      I => D(2),
      O => N3929
    );
  N3931_31 : X_BUF
    port map (
      I => D(3),
      O => N3931
    );
  N3933_32 : X_BUF
    port map (
      I => D(4),
      O => N3933
    );
  MR_0_0_IBUF_33 : X_BUF
    port map (
      I => MR_0(0),
      O => MR_0_0_IBUF
    );
  MR_2_0_IBUF_34 : X_BUF
    port map (
      I => MR_2(0),
      O => MR_2_0_IBUF
    );
  MR_1_0_IBUF_35 : X_BUF
    port map (
      I => MR_1(0),
      O => MR_1_0_IBUF
    );
  MR_1_1_IBUF_36 : X_BUF
    port map (
      I => MR_1(1),
      O => MR_1_1_IBUF
    );
  MR_0_1_IBUF_37 : X_BUF
    port map (
      I => MR_0(1),
      O => MR_0_1_IBUF
    );
  MR_2_1_IBUF_38 : X_BUF
    port map (
      I => MR_2(1),
      O => MR_2_1_IBUF
    );
  MR_0_2_IBUF_39 : X_BUF
    port map (
      I => MR_0(2),
      O => MR_0_2_IBUF
    );
  MR_2_2_IBUF_40 : X_BUF
    port map (
      I => MR_2(2),
      O => MR_2_2_IBUF
    );
  MR_1_2_IBUF_41 : X_BUF
    port map (
      I => MR_1(2),
      O => MR_1_2_IBUF
    );
  MR_0_3_IBUF_42 : X_BUF
    port map (
      I => MR_0(3),
      O => MR_0_3_IBUF
    );
  MR_2_3_IBUF_43 : X_BUF
    port map (
      I => MR_2(3),
      O => MR_2_3_IBUF
    );
  MR_1_3_IBUF_44 : X_BUF
    port map (
      I => MR_1(3),
      O => MR_1_3_IBUF
    );
  MR_0_4_IBUF_45 : X_BUF
    port map (
      I => MR_0(4),
      O => MR_0_4_IBUF
    );
  MR_2_4_IBUF_46 : X_BUF
    port map (
      I => MR_2(4),
      O => MR_2_4_IBUF
    );
  MR_1_4_IBUF_47 : X_BUF
    port map (
      I => MR_1(4),
      O => MR_1_4_IBUF
    );
  MR_0_5_IBUF_48 : X_BUF
    port map (
      I => MR_0(5),
      O => MR_0_5_IBUF
    );
  MR_2_5_IBUF_49 : X_BUF
    port map (
      I => MR_2(5),
      O => MR_2_5_IBUF
    );
  MR_1_5_IBUF_50 : X_BUF
    port map (
      I => MR_1(5),
      O => MR_1_5_IBUF
    );
  MR_0_6_IBUF_51 : X_BUF
    port map (
      I => MR_0(6),
      O => MR_0_6_IBUF
    );
  MR_2_6_IBUF_52 : X_BUF
    port map (
      I => MR_2(6),
      O => MR_2_6_IBUF
    );
  MR_1_6_IBUF_53 : X_BUF
    port map (
      I => MR_1(6),
      O => MR_1_6_IBUF
    );
  MR_0_7_IBUF_54 : X_BUF
    port map (
      I => MR_0(7),
      O => MR_0_7_IBUF
    );
  MR_2_7_IBUF_55 : X_BUF
    port map (
      I => MR_2(7),
      O => MR_2_7_IBUF
    );
  MR_1_7_IBUF_56 : X_BUF
    port map (
      I => MR_1(7),
      O => MR_1_7_IBUF