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xilinx xc9572 cpld 实现的伺服电机控制器

  signal Q_7_TRST : STD_LOGIC; 
  signal Q_7_D : STD_LOGIC; 
  signal Q_7_D1 : STD_LOGIC; 
  signal Q_7_D2 : STD_LOGIC; 
  signal Q_8_Q : STD_LOGIC; 
  signal Q_8_BUFOE_OUT : STD_LOGIC; 
  signal Q_8_TRST : STD_LOGIC; 
  signal Q_8_D : STD_LOGIC; 
  signal Q_8_D1 : STD_LOGIC; 
  signal Q_8_D2 : STD_LOGIC; 
  signal Q_9_Q : STD_LOGIC; 
  signal Q_9_BUFOE_OUT : STD_LOGIC; 
  signal Q_9_TRST : STD_LOGIC; 
  signal Q_9_D : STD_LOGIC; 
  signal Q_9_D1 : STD_LOGIC; 
  signal Q_9_D2 : STD_LOGIC; 
  signal Q_10_Q : STD_LOGIC; 
  signal Q_10_BUFOE_OUT : STD_LOGIC; 
  signal Q_10_TRST : STD_LOGIC; 
  signal Q_10_D : STD_LOGIC; 
  signal Q_10_D1 : STD_LOGIC; 
  signal Q_10_D2 : STD_LOGIC; 
  signal NlwInverterSignal_CS1_OBUF_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CS1_OBUF_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CS1_OBUF_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CS1_OBUF_D2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_CS1_OBUF_D2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_M1CLR_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_M1CLR_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_M1CLR_OBUF_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_M1CLR_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_M1CLR_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_M1CLR_OBUF_D2_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_M1CLR_OBUF_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_M1CLR_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_M1CLR_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_M1CLR_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_M1CLR_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_M1CLR_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_M1CLR_OBUF_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_M1CLR_OBUF_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_M1CLR_OBUF_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_M1CLR_OBUF_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_M1PS_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_M1PS_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_M1PS_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_M1PS_OBUF_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_M1PS_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_M1PS_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_M1PS_OBUF_D2_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_M1PS_OBUF_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_M1PS_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_M1PS_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_M1PS_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_M1PS_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_M1PS_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_M1PS_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_M1PS_OBUF_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_M1PS_OBUF_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_M1PS_OBUF_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_M1PS_OBUF_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_M1SG_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_M1SG_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_M1SG_OBUF_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_M1SG_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_M1SG_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_M1SG_OBUF_D2_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_M1SG_OBUF_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_M1SG_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_M1SG_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_M1SG_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_M1SG_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_M1SG_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_M1SG_OBUF_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_M1SG_OBUF_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_M1SG_OBUF_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_M1SG_OBUF_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_M2CLR_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_M2CLR_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_M2CLR_OBUF_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_M2CLR_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_M2CLR_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_M2CLR_OBUF_D2_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_M2CLR_OBUF_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_M2CLR_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_M2CLR_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_M2CLR_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_M2CLR_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_M2CLR_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_M2CLR_OBUF_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_M2CLR_OBUF_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_M2CLR_OBUF_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_M2CLR_OBUF_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_M2PS_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_M2PS_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_M2PS_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_M2PS_OBUF_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_M2PS_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_M2PS_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_M2PS_OBUF_D2_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_M2PS_OBUF_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_M2PS_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_M2PS_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_M2PS_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_M2PS_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_M2PS_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_M2PS_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_M2PS_OBUF_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_M2PS_OBUF_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_M2PS_OBUF_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_M2PS_OBUF_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_M2SG_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_M2SG_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_M2SG_OBUF_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_M2SG_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_M2SG_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_M2SG_OBUF_D2_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_M2SG_OBUF_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_M2SG_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_M2SG_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_M2SG_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_M2SG_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_M2SG_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_M2SG_OBUF_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_M2SG_OBUF_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_M2SG_OBUF_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_M2SG_OBUF_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_PC1ON_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_PC1ON_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_PC1ON_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_PC1ON_OBUF_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_PC1ON_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_PC1ON_OBUF_D2_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_PC1ON_OBUF_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_PC1ON_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_PC1ON_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_PC1ON_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_PC1ON_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_PC1ON_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_PC1ON_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_PC1ON_OBUF_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_PC1ON_OBUF_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_PC1ON_OBUF_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_PC2ON_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_PC2ON_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_PC2ON_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_PC2ON_OBUF_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_PC2ON_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_PC2ON_OBUF_D2_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_PC2ON_OBUF_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_PC2ON_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_PC2ON_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_PC2ON_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_PC2ON_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_PC2ON_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_PC2ON_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_PC2ON_OBUF_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_PC2ON_OBUF_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_PC2ON_OBUF_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REL0_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REL0_OBUF_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REL0_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REL0_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_REL0_OBUF_D2_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_REL0_OBUF_D2_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_REL0_OBUF_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_REL0_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REL0_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REL0_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REL0_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_REL0_OBUF_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_REL0_OBUF_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_REL0_OBUF_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_REL0_OBUF_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REL0_OBUF_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SEN0_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SEN0_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SEN0_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SEN0_OBUF_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SEN0_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SEN0_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_SEN0_OBUF_D2_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_SEN0_OBUF_D2_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_SEN0_OBUF_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_SEN0_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SEN0_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SEN0_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SEN0_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SEN0_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SEN0_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_SEN0_OBUF_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_SEN0_OBUF_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_SEN0_OBUF_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_SEN0_OBUF_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SEN0_OBUF_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SEN1_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SEN1_OBUF_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SEN1_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SEN1_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_SEN1_OBUF_D2_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_SEN1_OBUF_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_SEN1_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SEN1_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SEN1_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SEN1_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_SEN1_OBUF_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_SEN1_OBUF_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_SEN1_OBUF_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SEN1_OBUF_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SEN2_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SEN2_OBUF_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SEN2_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SEN2_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_SEN2_OBUF_D2_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_SEN2_OBUF_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_SEN2_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SEN2_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SEN2_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SEN2_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_SEN2_OBUF_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_SEN2_OBUF_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_SEN2_OBUF_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SEN2_OBUF_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SPD2A_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SPD2A_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SPD2A_OBUF_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SPD2A_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SPD2A_OBUF_D2_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_SPD2A_OBUF_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_SPD2A_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SPD2A_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SPD2A_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SPD2A_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SPD2A_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_SPD2A_OBUF_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_SPD2A_OBUF_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SPD2A_OBUF_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SPDA1_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SPDA1_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SPDA1_OBUF_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SPDA1_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SPDA1_OBUF_D2_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_SPDA1_OBUF_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_SPDA1_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SPDA1_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SPDA1_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SPDA1_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SPDA1_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_SPDA1_OBUF_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_SPDA1_OBUF_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SPDA1_OBUF_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB1_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB1_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB1_OBUF_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB1_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB1_OBUF_D2_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB1_OBUF_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB1_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB1_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB1_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB1_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB1_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB1_OBUF_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB1_OBUF_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB1_OBUF_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB2_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB2_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB2_OBUF_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB2_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB2_OBUF_D2_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB2_OBUF_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB2_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB2_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB2_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB2_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB2_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB2_OBUF_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB2_OBUF_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SPDB2_OBUF_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_D_0_IOBUFE_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_D_0_IOBUFE_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_D_0_IOBUFE_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_D_0_IOBUFE_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_D_0_IOBUFE_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_D_1_IOBUFE_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_D_1_IOBUFE_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_D_1_IOBUFE_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_D_1_IOBUFE_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_D_1_IOBUFE_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_D_2_IOBUFE_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_D_2_IOBUFE_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_D_2_IOBUFE_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_D_2_IOBUFE_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_D_2_IOBUFE_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_D_3_BUFR_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_D_3_BUFR_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_D_3_BUFR_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_D_3_BUFR_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_D_4_BUFR_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_D_4_BUFR_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_D_4_BUFR_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_D_4_BUFR_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_D_5_BUFR_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_D_5_BUFR_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_D_5_BUFR_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_D_5_BUFR_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_D_6_BUFR_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_D_6_BUFR_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_D_6_BUFR_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_D_6_BUFR_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_D_7_BUFR_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_D_7_BUFR_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_D_7_BUFR_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_D_7_BUFR_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q41_0_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q41_0_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q41_0_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q41_0_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q4_0_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q4_0_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q4_0_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q4_0_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q41_1_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q41_1_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q41_1_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q41_1_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q41_1_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q4_1_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q4_1_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q4_1_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q4_1_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_57_Q4_1_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CLR0_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CLR0_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_CLR0_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_CLR0_D2_PT_0_IN5 : STD_LOGIC;