top_timesim.vhd

xilinx xc9572 cpld 实现的伺服电机控制器

  signal D_0_IOBUFE_D1 : STD_LOGIC; 
  signal D_0_IOBUFE_D2 : STD_LOGIC; 
  signal XLXN_8_0_Q : STD_LOGIC; 
  signal D_0_IOBUFE_D2_PT_0 : STD_LOGIC; 
  signal D_0_IOBUFE_D2_PT_1 : STD_LOGIC; 
  signal D_0_IOBUFE_D2_PT_2 : STD_LOGIC; 
  signal D_0_IOBUFE_D2_PT_3 : STD_LOGIC; 
  signal D_1_IOBUFE_Q : STD_LOGIC; 
  signal D_1_IOBUFE_BUFOE_OUT : STD_LOGIC; 
  signal D_1_IOBUFE_TRST : STD_LOGIC; 
  signal D_1_IOBUFE_D : STD_LOGIC; 
  signal D_1_IOBUFE_D1 : STD_LOGIC; 
  signal D_1_IOBUFE_D2 : STD_LOGIC; 
  signal XLXN_8_1_Q : STD_LOGIC; 
  signal D_1_IOBUFE_D2_PT_0 : STD_LOGIC; 
  signal D_1_IOBUFE_D2_PT_1 : STD_LOGIC; 
  signal D_1_IOBUFE_D2_PT_2 : STD_LOGIC; 
  signal D_1_IOBUFE_D2_PT_3 : STD_LOGIC; 
  signal D_2_IOBUFE_Q : STD_LOGIC; 
  signal D_2_IOBUFE_BUFOE_OUT : STD_LOGIC; 
  signal D_2_IOBUFE_TRST : STD_LOGIC; 
  signal D_2_IOBUFE_D : STD_LOGIC; 
  signal D_2_IOBUFE_D1 : STD_LOGIC; 
  signal D_2_IOBUFE_D2 : STD_LOGIC; 
  signal XLXN_8_2_Q : STD_LOGIC; 
  signal D_2_IOBUFE_D2_PT_0 : STD_LOGIC; 
  signal D_2_IOBUFE_D2_PT_1 : STD_LOGIC; 
  signal D_2_IOBUFE_D2_PT_2 : STD_LOGIC; 
  signal D_2_IOBUFE_D2_PT_3 : STD_LOGIC; 
  signal D_3_BUFR_Q : STD_LOGIC; 
  signal D_3_BUFR : STD_LOGIC; 
  signal D_3_BUFR_D : STD_LOGIC; 
  signal D_3_BUFR_D1 : STD_LOGIC; 
  signal D_3_BUFR_D2 : STD_LOGIC; 
  signal XLXN_8_3_FBK : STD_LOGIC; 
  signal D_3_BUFR_D2_PT_0 : STD_LOGIC; 
  signal D_3_BUFR_D2_PT_1 : STD_LOGIC; 
  signal D_3_BUFR_D2_PT_2 : STD_LOGIC; 
  signal D_3_BUFR_D2_PT_3 : STD_LOGIC; 
  signal D_4_BUFR_Q : STD_LOGIC; 
  signal D_4_BUFR : STD_LOGIC; 
  signal D_4_BUFR_D : STD_LOGIC; 
  signal D_4_BUFR_D1 : STD_LOGIC; 
  signal D_4_BUFR_D2 : STD_LOGIC; 
  signal XLXN_8_4_Q : STD_LOGIC; 
  signal D_4_BUFR_D2_PT_0 : STD_LOGIC; 
  signal D_4_BUFR_D2_PT_1 : STD_LOGIC; 
  signal D_4_BUFR_D2_PT_2 : STD_LOGIC; 
  signal D_4_BUFR_D2_PT_3 : STD_LOGIC; 
  signal D_5_BUFR_Q : STD_LOGIC; 
  signal D_5_BUFR : STD_LOGIC; 
  signal D_5_BUFR_D : STD_LOGIC; 
  signal D_5_BUFR_D1 : STD_LOGIC; 
  signal D_5_BUFR_D2 : STD_LOGIC; 
  signal XLXN_8_5_FBK : STD_LOGIC; 
  signal D_5_BUFR_D2_PT_0 : STD_LOGIC; 
  signal D_5_BUFR_D2_PT_1 : STD_LOGIC; 
  signal D_5_BUFR_D2_PT_2 : STD_LOGIC; 
  signal D_5_BUFR_D2_PT_3 : STD_LOGIC; 
  signal D_6_BUFR_Q : STD_LOGIC; 
  signal D_6_BUFR : STD_LOGIC; 
  signal D_6_BUFR_D : STD_LOGIC; 
  signal D_6_BUFR_D1 : STD_LOGIC; 
  signal D_6_BUFR_D2 : STD_LOGIC; 
  signal XLXN_8_6_Q : STD_LOGIC; 
  signal D_6_BUFR_D2_PT_0 : STD_LOGIC; 
  signal D_6_BUFR_D2_PT_1 : STD_LOGIC; 
  signal D_6_BUFR_D2_PT_2 : STD_LOGIC; 
  signal D_6_BUFR_D2_PT_3 : STD_LOGIC; 
  signal D_7_BUFR_Q : STD_LOGIC; 
  signal D_7_BUFR : STD_LOGIC; 
  signal D_7_BUFR_D : STD_LOGIC; 
  signal D_7_BUFR_D1 : STD_LOGIC; 
  signal D_7_BUFR_D2 : STD_LOGIC; 
  signal XLXN_8_7_FBK : STD_LOGIC; 
  signal D_7_BUFR_D2_PT_0 : STD_LOGIC; 
  signal D_7_BUFR_D2_PT_1 : STD_LOGIC; 
  signal D_7_BUFR_D2_PT_2 : STD_LOGIC; 
  signal D_7_BUFR_D2_PT_3 : STD_LOGIC; 
  signal XLXI_57_Q41_0_Q : STD_LOGIC; 
  signal XLXI_57_Q41_0_FBK : STD_LOGIC; 
  signal XLXI_57_Q41_0_D : STD_LOGIC; 
  signal XLXI_57_Q41_0_tsimcreated_xor_Q : STD_LOGIC; 
  signal XLXI_57_Q41_0_RSTF : STD_LOGIC; 
  signal XLXI_57_Q41_0_tsimcreated_prld_Q : STD_LOGIC; 
  signal XLXI_57_Q41_0_CLKF : STD_LOGIC; 
  signal XLXI_57_Q41_0_D1 : STD_LOGIC; 
  signal XLXI_57_Q41_0_D2 : STD_LOGIC; 
  signal XLXI_57_Q41_0_D2_PT_0 : STD_LOGIC; 
  signal XLXI_57_Q41_0_D2_PT_1 : STD_LOGIC; 
  signal XLXI_57_Q41_2_XLXI_57_Q41_2_CLKF_INT_FBK : STD_LOGIC; 
  signal CLR1 : STD_LOGIC; 
  signal XLXI_57_Q4_0_Q : STD_LOGIC; 
  signal XLXI_57_Q4_0_FBK : STD_LOGIC; 
  signal XLXI_57_Q4_0_D : STD_LOGIC; 
  signal XLXI_57_Q4_0_tsimcreated_xor_Q : STD_LOGIC; 
  signal XLXI_57_Q4_0_RSTF : STD_LOGIC; 
  signal XLXI_57_Q4_0_tsimcreated_prld_Q : STD_LOGIC; 
  signal XLXI_57_Q4_0_CLKF : STD_LOGIC; 
  signal XLXI_57_Q4_0_D1 : STD_LOGIC; 
  signal XLXI_57_Q4_0_D2 : STD_LOGIC; 
  signal XLXI_57_Q4_0_D2_PT_0 : STD_LOGIC; 
  signal XLXI_57_Q4_0_D2_PT_1 : STD_LOGIC; 
  signal XLXI_57_Q4_2_XLXI_57_Q4_2_CLKF_INT_FBK : STD_LOGIC; 
  signal CLR0 : STD_LOGIC; 
  signal XLXI_57_Q41_1_Q : STD_LOGIC; 
  signal XLXI_57_Q41_1_FBK : STD_LOGIC; 
  signal XLXI_57_Q41_1_D : STD_LOGIC; 
  signal XLXI_57_Q41_1_tsimcreated_xor_Q : STD_LOGIC; 
  signal XLXI_57_Q41_1_RSTF : STD_LOGIC; 
  signal XLXI_57_Q41_1_tsimcreated_prld_Q : STD_LOGIC; 
  signal XLXI_57_Q41_1_CLKF : STD_LOGIC; 
  signal XLXI_57_Q41_1_D1 : STD_LOGIC; 
  signal XLXI_57_Q41_1_D2 : STD_LOGIC; 
  signal XLXI_57_Q41_1_D2_PT_0 : STD_LOGIC; 
  signal XLXI_57_Q41_1_D2_PT_1 : STD_LOGIC; 
  signal XLXI_57_Q4_1_Q : STD_LOGIC; 
  signal XLXI_57_Q4_1_FBK : STD_LOGIC; 
  signal XLXI_57_Q4_1_D : STD_LOGIC; 
  signal XLXI_57_Q4_1_tsimcreated_xor_Q : STD_LOGIC; 
  signal XLXI_57_Q4_1_RSTF : STD_LOGIC; 
  signal XLXI_57_Q4_1_tsimcreated_prld_Q : STD_LOGIC; 
  signal XLXI_57_Q4_1_CLKF : STD_LOGIC; 
  signal XLXI_57_Q4_1_D1 : STD_LOGIC; 
  signal XLXI_57_Q4_1_D2 : STD_LOGIC; 
  signal XLXI_57_Q4_1_D2_PT_0 : STD_LOGIC; 
  signal XLXI_57_Q4_1_D2_PT_1 : STD_LOGIC; 
  signal CLR0_Q : STD_LOGIC; 
  signal CLR0_FBK : STD_LOGIC; 
  signal CLR0_D : STD_LOGIC; 
  signal CLR0_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLR0_RSTF : STD_LOGIC; 
  signal CLR0_tsimcreated_prld_Q : STD_LOGIC; 
  signal CLR0_CLKF : STD_LOGIC; 
  signal CLR0_D1 : STD_LOGIC; 
  signal CLR0_D2 : STD_LOGIC; 
  signal CLR0_D2_PT_0 : STD_LOGIC; 
  signal CLR0_D2_PT_1 : STD_LOGIC; 
  signal CLR1_Q : STD_LOGIC; 
  signal CLR1_FBK : STD_LOGIC; 
  signal CLR1_D : STD_LOGIC; 
  signal CLR1_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLR1_RSTF : STD_LOGIC; 
  signal CLR1_tsimcreated_prld_Q : STD_LOGIC; 
  signal CLR1_CLKF : STD_LOGIC; 
  signal CLR1_D1 : STD_LOGIC; 
  signal CLR1_D2 : STD_LOGIC; 
  signal CLR1_D2_PT_0 : STD_LOGIC; 
  signal CLR1_D2_PT_1 : STD_LOGIC; 
  signal CSA2_Q : STD_LOGIC; 
  signal CSA2 : STD_LOGIC; 
  signal CSA2_FBK : STD_LOGIC; 
  signal CSA2_D : STD_LOGIC; 
  signal CSA2_tsimcreated_xor_Q : STD_LOGIC; 
  signal CSA2_RSTF : STD_LOGIC; 
  signal CSA2_tsimcreated_prld_Q : STD_LOGIC; 
  signal CSA2_CLKF : STD_LOGIC; 
  signal CSA2_D1 : STD_LOGIC; 
  signal CSA2_D2 : STD_LOGIC; 
  signal CSA2_D2_PT_0 : STD_LOGIC; 
  signal CSA2_D2_PT_1 : STD_LOGIC; 
  signal XLXI_57_Q41_2_Q : STD_LOGIC; 
  signal XLXI_57_Q41_2_FBK : STD_LOGIC; 
  signal XLXI_57_Q41_2_D : STD_LOGIC; 
  signal XLXI_57_Q41_2_tsimcreated_xor_Q : STD_LOGIC; 
  signal XLXI_57_Q41_2_RSTF : STD_LOGIC; 
  signal XLXI_57_Q41_2_tsimcreated_prld_Q : STD_LOGIC; 
  signal XLXI_57_Q41_2_CLKF : STD_LOGIC; 
  signal XLXI_57_Q41_2_D1 : STD_LOGIC; 
  signal XLXI_57_Q41_2_D2 : STD_LOGIC; 
  signal XLXI_57_Q41_2_D2_PT_0 : STD_LOGIC; 
  signal XLXI_57_Q41_2_D2_PT_1 : STD_LOGIC; 
  signal XLXI_57_Q4_2_Q : STD_LOGIC; 
  signal XLXI_57_Q4_2_FBK : STD_LOGIC; 
  signal XLXI_57_Q4_2_D : STD_LOGIC; 
  signal XLXI_57_Q4_2_tsimcreated_xor_Q : STD_LOGIC; 
  signal XLXI_57_Q4_2_RSTF : STD_LOGIC; 
  signal XLXI_57_Q4_2_tsimcreated_prld_Q : STD_LOGIC; 
  signal XLXI_57_Q4_2_CLKF : STD_LOGIC; 
  signal XLXI_57_Q4_2_D1 : STD_LOGIC; 
  signal XLXI_57_Q4_2_D2 : STD_LOGIC; 
  signal XLXI_57_Q4_2_D2_PT_0 : STD_LOGIC; 
  signal XLXI_57_Q4_2_D2_PT_1 : STD_LOGIC; 
  signal CSA1_Q : STD_LOGIC; 
  signal CSA1 : STD_LOGIC; 
  signal CSA1_FBK : STD_LOGIC; 
  signal CSA1_D : STD_LOGIC; 
  signal CSA1_tsimcreated_xor_Q : STD_LOGIC; 
  signal CSA1_RSTF : STD_LOGIC; 
  signal CSA1_tsimcreated_prld_Q : STD_LOGIC; 
  signal CSA1_CLKF : STD_LOGIC; 
  signal CSA1_D1 : STD_LOGIC; 
  signal CSA1_D2 : STD_LOGIC; 
  signal CSA1_D2_PT_0 : STD_LOGIC; 
  signal CSA1_D2_PT_1 : STD_LOGIC; 
  signal XLXI_57_Q41_3_Q : STD_LOGIC; 
  signal XLXI_57_Q41_3_FBK : STD_LOGIC; 
  signal XLXI_57_Q41_3_D : STD_LOGIC; 
  signal XLXI_57_Q41_3_tsimcreated_xor_Q : STD_LOGIC; 
  signal XLXI_57_Q41_3_RSTF : STD_LOGIC; 
  signal XLXI_57_Q41_3_tsimcreated_prld_Q : STD_LOGIC; 
  signal XLXI_57_Q41_3_CLKF : STD_LOGIC; 
  signal XLXI_57_Q41_3_D1 : STD_LOGIC; 
  signal XLXI_57_Q41_3_D2 : STD_LOGIC; 
  signal XLXI_57_Q41_3_D2_PT_0 : STD_LOGIC; 
  signal XLXI_57_Q41_3_D2_PT_1 : STD_LOGIC; 
  signal XLXI_57_Q4_3_Q : STD_LOGIC; 
  signal XLXI_57_Q4_3_FBK : STD_LOGIC; 
  signal XLXI_57_Q4_3_D : STD_LOGIC; 
  signal XLXI_57_Q4_3_tsimcreated_xor_Q : STD_LOGIC; 
  signal XLXI_57_Q4_3_RSTF : STD_LOGIC; 
  signal XLXI_57_Q4_3_tsimcreated_prld_Q : STD_LOGIC; 
  signal XLXI_57_Q4_3_CLKF : STD_LOGIC; 
  signal XLXI_57_Q4_3_D1 : STD_LOGIC; 
  signal XLXI_57_Q4_3_D2 : STD_LOGIC; 
  signal XLXI_57_Q4_3_D2_PT_0 : STD_LOGIC; 
  signal XLXI_57_Q4_3_D2_PT_1 : STD_LOGIC; 
  signal CS_U_Q : STD_LOGIC; 
  signal CS_U : STD_LOGIC; 
  signal CS_U_FBK : STD_LOGIC; 
  signal CS_U_D : STD_LOGIC; 
  signal CS_U_tsimcreated_xor_Q : STD_LOGIC; 
  signal CS_U_RSTF : STD_LOGIC; 
  signal CS_U_tsimcreated_prld_Q : STD_LOGIC; 
  signal CS_U_CLKF : STD_LOGIC; 
  signal CS_U_D1 : STD_LOGIC; 
  signal CS_U_D2 : STD_LOGIC; 
  signal CS_U_D2_PT_0 : STD_LOGIC; 
  signal CS_U_D2_PT_1 : STD_LOGIC; 
  signal ALMR_OBUF_Q : STD_LOGIC; 
  signal ALMR_OBUF_D : STD_LOGIC; 
  signal ALMR_OBUF_D1 : STD_LOGIC; 
  signal ALMR_OBUF_D2 : STD_LOGIC; 
  signal XLXN_8_0_Q_16 : STD_LOGIC; 
  signal XLXN_8_0_RSTF : STD_LOGIC; 
  signal XLXN_8_0_SETF : STD_LOGIC; 
  signal XLXN_8_0_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal XLXN_8_0_tsimcreated_prld_Q : STD_LOGIC; 
  signal XLXN_8_0_D : STD_LOGIC; 
  signal XLXN_8_0_CLKF : STD_LOGIC; 
  signal XLXN_8_0_D1 : STD_LOGIC; 
  signal XLXN_8_0_D2 : STD_LOGIC; 
  signal XLXN_8_1_Q_17 : STD_LOGIC; 
  signal XLXN_8_1_RSTF : STD_LOGIC; 
  signal XLXN_8_1_SETF : STD_LOGIC; 
  signal XLXN_8_1_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal XLXN_8_1_tsimcreated_prld_Q : STD_LOGIC; 
  signal XLXN_8_1_D : STD_LOGIC; 
  signal XLXN_8_1_CLKF : STD_LOGIC; 
  signal XLXN_8_1_D1 : STD_LOGIC; 
  signal XLXN_8_1_D2 : STD_LOGIC; 
  signal XLXN_8_2_Q_18 : STD_LOGIC; 
  signal XLXN_8_2_RSTF : STD_LOGIC; 
  signal XLXN_8_2_SETF : STD_LOGIC; 
  signal XLXN_8_2_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal XLXN_8_2_tsimcreated_prld_Q : STD_LOGIC; 
  signal XLXN_8_2_D : STD_LOGIC; 
  signal XLXN_8_2_CLKF : STD_LOGIC; 
  signal XLXN_8_2_D1 : STD_LOGIC; 
  signal XLXN_8_2_D2 : STD_LOGIC; 
  signal XLXN_8_3_Q : STD_LOGIC; 
  signal XLXN_8_3_RSTF : STD_LOGIC; 
  signal XLXN_8_3_SETF : STD_LOGIC; 
  signal XLXN_8_3_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal XLXN_8_3_tsimcreated_prld_Q : STD_LOGIC; 
  signal XLXN_8_3_D : STD_LOGIC; 
  signal XLXN_8_3_CLKF : STD_LOGIC; 
  signal XLXN_8_3_D1 : STD_LOGIC; 
  signal XLXN_8_3_D2 : STD_LOGIC; 
  signal XLXN_8_4_Q_19 : STD_LOGIC; 
  signal XLXN_8_4_RSTF : STD_LOGIC; 
  signal XLXN_8_4_SETF : STD_LOGIC; 
  signal XLXN_8_4_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal XLXN_8_4_tsimcreated_prld_Q : STD_LOGIC; 
  signal XLXN_8_4_D : STD_LOGIC; 
  signal XLXN_8_4_CLKF : STD_LOGIC; 
  signal XLXN_8_4_D1 : STD_LOGIC; 
  signal XLXN_8_4_D2 : STD_LOGIC; 
  signal XLXN_8_5_Q : STD_LOGIC; 
  signal XLXN_8_5_RSTF : STD_LOGIC; 
  signal XLXN_8_5_SETF : STD_LOGIC; 
  signal XLXN_8_5_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal XLXN_8_5_tsimcreated_prld_Q : STD_LOGIC; 
  signal XLXN_8_5_D : STD_LOGIC; 
  signal XLXN_8_5_CLKF : STD_LOGIC; 
  signal XLXN_8_5_D1 : STD_LOGIC; 
  signal XLXN_8_5_D2 : STD_LOGIC; 
  signal XLXN_8_6_Q_20 : STD_LOGIC; 
  signal XLXN_8_6_RSTF : STD_LOGIC; 
  signal XLXN_8_6_SETF : STD_LOGIC; 
  signal XLXN_8_6_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal XLXN_8_6_tsimcreated_prld_Q : STD_LOGIC; 
  signal XLXN_8_6_D : STD_LOGIC; 
  signal XLXN_8_6_CLKF : STD_LOGIC; 
  signal XLXN_8_6_D1 : STD_LOGIC; 
  signal XLXN_8_6_D2 : STD_LOGIC; 
  signal XLXN_8_7_Q : STD_LOGIC; 
  signal XLXN_8_7_RSTF : STD_LOGIC; 
  signal XLXN_8_7_SETF : STD_LOGIC; 
  signal XLXN_8_7_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal XLXN_8_7_tsimcreated_prld_Q : STD_LOGIC; 
  signal XLXN_8_7_D : STD_LOGIC; 
  signal XLXN_8_7_CLKF : STD_LOGIC; 
  signal XLXN_8_7_D1 : STD_LOGIC; 
  signal XLXN_8_7_D2 : STD_LOGIC; 
  signal UART0_OBUF_Q : STD_LOGIC; 
  signal UART0_OBUF_D : STD_LOGIC; 
  signal UART0_OBUF_D1 : STD_LOGIC; 
  signal UART0_OBUF_D2 : STD_LOGIC; 
  signal UART0_OBUF_D2_PT_0 : STD_LOGIC; 
  signal UART0_OBUF_D2_PT_1 : STD_LOGIC; 
  signal UART0_OBUF_D2_PT_2 : STD_LOGIC; 
  signal CLK8_IBUF_BUF0_Q : STD_LOGIC; 
  signal CLK8_IBUF_BUF0_D : STD_LOGIC; 
  signal CLK8_IBUF_BUF0_D1 : STD_LOGIC; 
  signal CLK8_IBUF_BUF0_D2 : STD_LOGIC; 
  signal INT_L0_IBUF_BUF0_Q : STD_LOGIC; 
  signal INT_L0_IBUF_BUF0_D : STD_LOGIC; 
  signal INT_L0_IBUF_BUF0_D1 : STD_LOGIC; 
  signal INT_L0_IBUF_BUF0_D2 : STD_LOGIC; 
  signal XLXI_57_Q41_2_XLXI_57_Q41_2_CLKF_INT_Q : STD_LOGIC; 
  signal XLXI_57_Q41_2_XLXI_57_Q41_2_CLKF_INT_D : STD_LOGIC; 
  signal XLXI_57_Q41_2_XLXI_57_Q41_2_CLKF_INT_D1 : STD_LOGIC; 
  signal XLXI_57_Q41_2_XLXI_57_Q41_2_CLKF_INT_D2 : STD_LOGIC; 
  signal XLXI_57_Q4_2_XLXI_57_Q4_2_CLKF_INT_Q : STD_LOGIC; 
  signal XLXI_57_Q4_2_XLXI_57_Q4_2_CLKF_INT_D : STD_LOGIC; 
  signal XLXI_57_Q4_2_XLXI_57_Q4_2_CLKF_INT_D1 : STD_LOGIC; 
  signal XLXI_57_Q4_2_XLXI_57_Q4_2_CLKF_INT_D2 : STD_LOGIC; 
  signal Q_6_Q : STD_LOGIC; 
  signal Q_6_BUFOE_OUT : STD_LOGIC; 
  signal Q_6_TRST : STD_LOGIC; 
  signal Q_6_D : STD_LOGIC; 
  signal Q_6_D1 : STD_LOGIC; 
  signal Q_6_D2 : STD_LOGIC; 
  signal Q_7_Q : STD_LOGIC; 
  signal Q_7_BUFOE_OUT : STD_LOGIC;