top_timesim.vhd

xilinx xc9572 cpld 实现的伺服电机控制器

-- Xilinx Vhdl netlist produced by netgen application (version G.35)
-- Command       : -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim top.nga top_timesim.vhd 
-- Input file    : top.nga
-- Output file   : top_timesim.vhd
-- Design name   : top.nga
-- # of Entities : 1
-- Xilinx        : D:/Xilinx
-- Device        : XC9572-10-TQ100 (Speed File: Version 3.0)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity top is
  port (
    CS : in STD_LOGIC := 'X'; 
    A2 : in STD_LOGIC := 'X'; 
    A1 : in STD_LOGIC := 'X'; 
    A0 : in STD_LOGIC := 'X'; 
    WR : in STD_LOGIC := 'X'; 
    RESET : in STD_LOGIC := 'X'; 
    MA1 : in STD_LOGIC := 'X'; 
    MB1 : in STD_LOGIC := 'X'; 
    MA0 : in STD_LOGIC := 'X'; 
    MB0 : in STD_LOGIC := 'X'; 
    MC0 : in STD_LOGIC := 'X'; 
    MC1 : in STD_LOGIC := 'X'; 
    RD : in STD_LOGIC := 'X'; 
    CLK8 : in STD_LOGIC := 'X'; 
    INT_L0 : in STD_LOGIC := 'X'; 
    CS1 : out STD_LOGIC; 
    M1CLR : out STD_LOGIC; 
    M1PS : out STD_LOGIC; 
    M1SG : out STD_LOGIC; 
    M2CLR : out STD_LOGIC; 
    M2PS : out STD_LOGIC; 
    M2SG : out STD_LOGIC; 
    PC1ON : out STD_LOGIC; 
    PC2ON : out STD_LOGIC; 
    REL0 : out STD_LOGIC; 
    SEN0 : out STD_LOGIC; 
    SEN1 : out STD_LOGIC; 
    SEN2 : out STD_LOGIC; 
    SPD2A : out STD_LOGIC; 
    SPDA1 : out STD_LOGIC; 
    SPDB1 : out STD_LOGIC; 
    SPDB2 : out STD_LOGIC; 
    ALMR : out STD_LOGIC; 
    UART0 : out STD_LOGIC; 
    CLK : out STD_LOGIC; 
    INT0 : out STD_LOGIC; 
    MR_0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    MR_2 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    MR_1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    D : inout STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end top;

architecture Structure of top is
  signal N3927 : STD_LOGIC; 
  signal N3925 : STD_LOGIC; 
  signal CS_IBUF : STD_LOGIC; 
  signal A2_IBUF : STD_LOGIC; 
  signal A1_IBUF : STD_LOGIC; 
  signal A0_IBUF : STD_LOGIC; 
  signal WR_IBUF : STD_LOGIC; 
  signal RESET_IBUF : STD_LOGIC; 
  signal N3937 : STD_LOGIC; 
  signal N3929 : STD_LOGIC; 
  signal N3931 : STD_LOGIC; 
  signal N3933 : STD_LOGIC; 
  signal MR_0_0_IBUF : STD_LOGIC; 
  signal MR_2_0_IBUF : STD_LOGIC; 
  signal MR_1_0_IBUF : STD_LOGIC; 
  signal MR_1_1_IBUF : STD_LOGIC; 
  signal MR_0_1_IBUF : STD_LOGIC; 
  signal MR_2_1_IBUF : STD_LOGIC; 
  signal MR_0_2_IBUF : STD_LOGIC; 
  signal MR_2_2_IBUF : STD_LOGIC; 
  signal MR_1_2_IBUF : STD_LOGIC; 
  signal MR_0_3_IBUF : STD_LOGIC; 
  signal MR_2_3_IBUF : STD_LOGIC; 
  signal MR_1_3_IBUF : STD_LOGIC; 
  signal MR_0_4_IBUF : STD_LOGIC; 
  signal MR_2_4_IBUF : STD_LOGIC; 
  signal MR_1_4_IBUF : STD_LOGIC; 
  signal MR_0_5_IBUF : STD_LOGIC; 
  signal MR_2_5_IBUF : STD_LOGIC; 
  signal MR_1_5_IBUF : STD_LOGIC; 
  signal MR_0_6_IBUF : STD_LOGIC; 
  signal MR_2_6_IBUF : STD_LOGIC; 
  signal MR_1_6_IBUF : STD_LOGIC; 
  signal MR_0_7_IBUF : STD_LOGIC; 
  signal MR_2_7_IBUF : STD_LOGIC; 
  signal MR_1_7_IBUF : STD_LOGIC; 
  signal MA1_IBUF : STD_LOGIC; 
  signal MB1_IBUF : STD_LOGIC; 
  signal MA0_IBUF : STD_LOGIC; 
  signal MB0_IBUF : STD_LOGIC; 
  signal MC0_IBUF : STD_LOGIC; 
  signal MC1_IBUF : STD_LOGIC; 
  signal RD_IBUF : STD_LOGIC; 
  signal CLK8_IBUF : STD_LOGIC; 
  signal INT_L0_IBUF : STD_LOGIC; 
  signal CS1_OBUF : STD_LOGIC; 
  signal M1CLR_OBUF_Q : STD_LOGIC; 
  signal M1PS_OBUF_Q : STD_LOGIC; 
  signal M1SG_OBUF_Q : STD_LOGIC; 
  signal M2CLR_OBUF_Q : STD_LOGIC; 
  signal M2PS_OBUF_Q : STD_LOGIC; 
  signal M2SG_OBUF_Q : STD_LOGIC; 
  signal PC1ON_OBUF_Q : STD_LOGIC; 
  signal PC2ON_OBUF_Q : STD_LOGIC; 
  signal REL0_OBUF_Q : STD_LOGIC; 
  signal SEN0_OBUF_Q : STD_LOGIC; 
  signal SEN1_OBUF_Q : STD_LOGIC; 
  signal SEN2_OBUF_Q : STD_LOGIC; 
  signal SPD2A_OBUF_Q : STD_LOGIC; 
  signal SPDA1_OBUF_Q : STD_LOGIC; 
  signal SPDB1_OBUF_Q : STD_LOGIC; 
  signal SPDB2_OBUF_Q : STD_LOGIC; 
  signal D_0_IOBUFE : STD_LOGIC; 
  signal D_0_IOBUFE_OE : STD_LOGIC; 
  signal D_1_IOBUFE : STD_LOGIC; 
  signal D_1_IOBUFE_OE : STD_LOGIC; 
  signal D_2_IOBUFE : STD_LOGIC; 
  signal D_2_IOBUFE_OE : STD_LOGIC; 
  signal D_3_IOBUFE : STD_LOGIC; 
  signal D_3_IOBUFE_OE : STD_LOGIC; 
  signal D_4_IOBUFE : STD_LOGIC; 
  signal D_4_IOBUFE_OE : STD_LOGIC; 
  signal D_5_OBUFE : STD_LOGIC; 
  signal D_5_OBUFE_OE : STD_LOGIC; 
  signal D_6_OBUFE : STD_LOGIC; 
  signal D_6_OBUFE_OE : STD_LOGIC; 
  signal D_7_IOBUFE : STD_LOGIC; 
  signal D_7_IOBUFE_OE : STD_LOGIC; 
  signal ALMR_OBUF : STD_LOGIC; 
  signal UART0_OBUF : STD_LOGIC; 
  signal CLK8_IBUF_BUF0 : STD_LOGIC; 
  signal INT_L0_IBUF_BUF0 : STD_LOGIC; 
  signal CS1_OBUF_Q : STD_LOGIC; 
  signal CS1_OBUF_D : STD_LOGIC; 
  signal CS1_OBUF_D1 : STD_LOGIC; 
  signal CS1_OBUF_D2 : STD_LOGIC; 
  signal M1CLR_OBUF_Q_0 : STD_LOGIC; 
  signal M1CLR_OBUF_FBK : STD_LOGIC; 
  signal M1CLR_OBUF_D : STD_LOGIC; 
  signal M1CLR_OBUF_tsimcreated_xor_Q : STD_LOGIC; 
  signal M1CLR_OBUF_RSTF : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal M1CLR_OBUF_tsimcreated_prld_Q : STD_LOGIC; 
  signal M1CLR_OBUF_CLKF : STD_LOGIC; 
  signal Gnd : STD_LOGIC; 
  signal Vcc : STD_LOGIC; 
  signal M1CLR_OBUF_D1 : STD_LOGIC; 
  signal M1CLR_OBUF_D2 : STD_LOGIC; 
  signal M1CLR_OBUF_D2_PT_0 : STD_LOGIC; 
  signal M1CLR_OBUF_D2_PT_1 : STD_LOGIC; 
  signal M1PS_OBUF_Q_1 : STD_LOGIC; 
  signal M1PS_OBUF_FBK : STD_LOGIC; 
  signal M1PS_OBUF_D : STD_LOGIC; 
  signal M1PS_OBUF_tsimcreated_xor_Q : STD_LOGIC; 
  signal M1PS_OBUF_RSTF : STD_LOGIC; 
  signal M1PS_OBUF_tsimcreated_prld_Q : STD_LOGIC; 
  signal M1PS_OBUF_CLKF : STD_LOGIC; 
  signal M1PS_OBUF_D1 : STD_LOGIC; 
  signal M1PS_OBUF_D2 : STD_LOGIC; 
  signal M1PS_OBUF_D2_PT_0 : STD_LOGIC; 
  signal M1PS_OBUF_D2_PT_1 : STD_LOGIC; 
  signal M1SG_OBUF_Q_2 : STD_LOGIC; 
  signal M1SG_OBUF_FBK : STD_LOGIC; 
  signal M1SG_OBUF_D : STD_LOGIC; 
  signal M1SG_OBUF_tsimcreated_xor_Q : STD_LOGIC; 
  signal M1SG_OBUF_RSTF : STD_LOGIC; 
  signal M1SG_OBUF_tsimcreated_prld_Q : STD_LOGIC; 
  signal M1SG_OBUF_CLKF : STD_LOGIC; 
  signal M1SG_OBUF_D1 : STD_LOGIC; 
  signal M1SG_OBUF_D2 : STD_LOGIC; 
  signal M1SG_OBUF_D2_PT_0 : STD_LOGIC; 
  signal M1SG_OBUF_D2_PT_1 : STD_LOGIC; 
  signal M2CLR_OBUF_Q_3 : STD_LOGIC; 
  signal M2CLR_OBUF_FBK : STD_LOGIC; 
  signal M2CLR_OBUF_D : STD_LOGIC; 
  signal M2CLR_OBUF_tsimcreated_xor_Q : STD_LOGIC; 
  signal M2CLR_OBUF_RSTF : STD_LOGIC; 
  signal M2CLR_OBUF_tsimcreated_prld_Q : STD_LOGIC; 
  signal M2CLR_OBUF_CLKF : STD_LOGIC; 
  signal M2CLR_OBUF_D1 : STD_LOGIC; 
  signal M2CLR_OBUF_D2 : STD_LOGIC; 
  signal M2CLR_OBUF_D2_PT_0 : STD_LOGIC; 
  signal M2CLR_OBUF_D2_PT_1 : STD_LOGIC; 
  signal M2PS_OBUF_Q_4 : STD_LOGIC; 
  signal M2PS_OBUF_FBK : STD_LOGIC; 
  signal M2PS_OBUF_D : STD_LOGIC; 
  signal M2PS_OBUF_tsimcreated_xor_Q : STD_LOGIC; 
  signal M2PS_OBUF_RSTF : STD_LOGIC; 
  signal M2PS_OBUF_tsimcreated_prld_Q : STD_LOGIC; 
  signal M2PS_OBUF_CLKF : STD_LOGIC; 
  signal M2PS_OBUF_D1 : STD_LOGIC; 
  signal M2PS_OBUF_D2 : STD_LOGIC; 
  signal M2PS_OBUF_D2_PT_0 : STD_LOGIC; 
  signal M2PS_OBUF_D2_PT_1 : STD_LOGIC; 
  signal M2SG_OBUF_Q_5 : STD_LOGIC; 
  signal M2SG_OBUF_FBK : STD_LOGIC; 
  signal M2SG_OBUF_D : STD_LOGIC; 
  signal M2SG_OBUF_tsimcreated_xor_Q : STD_LOGIC; 
  signal M2SG_OBUF_RSTF : STD_LOGIC; 
  signal M2SG_OBUF_tsimcreated_prld_Q : STD_LOGIC; 
  signal M2SG_OBUF_CLKF : STD_LOGIC; 
  signal M2SG_OBUF_D1 : STD_LOGIC; 
  signal M2SG_OBUF_D2 : STD_LOGIC; 
  signal M2SG_OBUF_D2_PT_0 : STD_LOGIC; 
  signal M2SG_OBUF_D2_PT_1 : STD_LOGIC; 
  signal PC1ON_OBUF_Q_6 : STD_LOGIC; 
  signal PC1ON_OBUF_FBK : STD_LOGIC; 
  signal PC1ON_OBUF_D : STD_LOGIC; 
  signal PC1ON_OBUF_tsimcreated_xor_Q : STD_LOGIC; 
  signal PC1ON_OBUF_RSTF : STD_LOGIC; 
  signal PC1ON_OBUF_tsimcreated_prld_Q : STD_LOGIC; 
  signal PC1ON_OBUF_CLKF : STD_LOGIC; 
  signal PC1ON_OBUF_D1 : STD_LOGIC; 
  signal PC1ON_OBUF_D2 : STD_LOGIC; 
  signal PC1ON_OBUF_D2_PT_0 : STD_LOGIC; 
  signal PC1ON_OBUF_D2_PT_1 : STD_LOGIC; 
  signal PC2ON_OBUF_Q_7 : STD_LOGIC; 
  signal PC2ON_OBUF_FBK : STD_LOGIC; 
  signal PC2ON_OBUF_D : STD_LOGIC; 
  signal PC2ON_OBUF_tsimcreated_xor_Q : STD_LOGIC; 
  signal PC2ON_OBUF_RSTF : STD_LOGIC; 
  signal PC2ON_OBUF_tsimcreated_prld_Q : STD_LOGIC; 
  signal PC2ON_OBUF_CLKF : STD_LOGIC; 
  signal PC2ON_OBUF_D1 : STD_LOGIC; 
  signal PC2ON_OBUF_D2 : STD_LOGIC; 
  signal PC2ON_OBUF_D2_PT_0 : STD_LOGIC; 
  signal PC2ON_OBUF_D2_PT_1 : STD_LOGIC; 
  signal REL0_OBUF_Q_8 : STD_LOGIC; 
  signal REL0_OBUF_FBK : STD_LOGIC; 
  signal REL0_OBUF_D : STD_LOGIC; 
  signal REL0_OBUF_tsimcreated_xor_Q : STD_LOGIC; 
  signal REL0_OBUF_RSTF : STD_LOGIC; 
  signal REL0_OBUF_tsimcreated_prld_Q : STD_LOGIC; 
  signal REL0_OBUF_CLKF : STD_LOGIC; 
  signal REL0_OBUF_D1 : STD_LOGIC; 
  signal REL0_OBUF_D2 : STD_LOGIC; 
  signal REL0_OBUF_D2_PT_0 : STD_LOGIC; 
  signal REL0_OBUF_D2_PT_1 : STD_LOGIC; 
  signal SEN0_OBUF_Q_9 : STD_LOGIC; 
  signal SEN0_OBUF_FBK : STD_LOGIC; 
  signal SEN0_OBUF_D : STD_LOGIC; 
  signal SEN0_OBUF_tsimcreated_xor_Q : STD_LOGIC; 
  signal SEN0_OBUF_RSTF : STD_LOGIC; 
  signal SEN0_OBUF_tsimcreated_prld_Q : STD_LOGIC; 
  signal SEN0_OBUF_CLKF : STD_LOGIC; 
  signal SEN0_OBUF_D1 : STD_LOGIC; 
  signal SEN0_OBUF_D2 : STD_LOGIC; 
  signal SEN0_OBUF_D2_PT_0 : STD_LOGIC; 
  signal SEN0_OBUF_D2_PT_1 : STD_LOGIC; 
  signal SEN1_OBUF_Q_10 : STD_LOGIC; 
  signal SEN1_OBUF_FBK : STD_LOGIC; 
  signal SEN1_OBUF_D : STD_LOGIC; 
  signal SEN1_OBUF_tsimcreated_xor_Q : STD_LOGIC; 
  signal SEN1_OBUF_RSTF : STD_LOGIC; 
  signal SEN1_OBUF_tsimcreated_prld_Q : STD_LOGIC; 
  signal SEN1_OBUF_CLKF : STD_LOGIC; 
  signal SEN1_OBUF_D1 : STD_LOGIC; 
  signal SEN1_OBUF_D2 : STD_LOGIC; 
  signal SEN1_OBUF_D2_PT_0 : STD_LOGIC; 
  signal SEN1_OBUF_D2_PT_1 : STD_LOGIC; 
  signal SEN2_OBUF_Q_11 : STD_LOGIC; 
  signal SEN2_OBUF_FBK : STD_LOGIC; 
  signal SEN2_OBUF_D : STD_LOGIC; 
  signal SEN2_OBUF_tsimcreated_xor_Q : STD_LOGIC; 
  signal SEN2_OBUF_RSTF : STD_LOGIC; 
  signal SEN2_OBUF_tsimcreated_prld_Q : STD_LOGIC; 
  signal SEN2_OBUF_CLKF : STD_LOGIC; 
  signal SEN2_OBUF_D1 : STD_LOGIC; 
  signal SEN2_OBUF_D2 : STD_LOGIC; 
  signal SEN2_OBUF_D2_PT_0 : STD_LOGIC; 
  signal SEN2_OBUF_D2_PT_1 : STD_LOGIC; 
  signal SPD2A_OBUF_Q_12 : STD_LOGIC; 
  signal SPD2A_OBUF_FBK : STD_LOGIC; 
  signal SPD2A_OBUF_D : STD_LOGIC; 
  signal SPD2A_OBUF_tsimcreated_xor_Q : STD_LOGIC; 
  signal SPD2A_OBUF_RSTF : STD_LOGIC; 
  signal SPD2A_OBUF_tsimcreated_prld_Q : STD_LOGIC; 
  signal SPD2A_OBUF_CLKF : STD_LOGIC; 
  signal SPD2A_OBUF_D1 : STD_LOGIC; 
  signal SPD2A_OBUF_D2 : STD_LOGIC; 
  signal SPD2A_OBUF_D2_PT_0 : STD_LOGIC; 
  signal SPD2A_OBUF_D2_PT_1 : STD_LOGIC; 
  signal SPDA1_OBUF_Q_13 : STD_LOGIC; 
  signal SPDA1_OBUF_FBK : STD_LOGIC; 
  signal SPDA1_OBUF_D : STD_LOGIC; 
  signal SPDA1_OBUF_tsimcreated_xor_Q : STD_LOGIC; 
  signal SPDA1_OBUF_RSTF : STD_LOGIC; 
  signal SPDA1_OBUF_tsimcreated_prld_Q : STD_LOGIC; 
  signal SPDA1_OBUF_CLKF : STD_LOGIC; 
  signal SPDA1_OBUF_D1 : STD_LOGIC; 
  signal SPDA1_OBUF_D2 : STD_LOGIC; 
  signal SPDA1_OBUF_D2_PT_0 : STD_LOGIC; 
  signal SPDA1_OBUF_D2_PT_1 : STD_LOGIC; 
  signal SPDB1_OBUF_Q_14 : STD_LOGIC; 
  signal SPDB1_OBUF_FBK : STD_LOGIC; 
  signal SPDB1_OBUF_D : STD_LOGIC; 
  signal SPDB1_OBUF_tsimcreated_xor_Q : STD_LOGIC; 
  signal SPDB1_OBUF_RSTF : STD_LOGIC; 
  signal SPDB1_OBUF_tsimcreated_prld_Q : STD_LOGIC; 
  signal SPDB1_OBUF_CLKF : STD_LOGIC; 
  signal SPDB1_OBUF_D1 : STD_LOGIC; 
  signal SPDB1_OBUF_D2 : STD_LOGIC; 
  signal SPDB1_OBUF_D2_PT_0 : STD_LOGIC; 
  signal SPDB1_OBUF_D2_PT_1 : STD_LOGIC; 
  signal SPDB2_OBUF_Q_15 : STD_LOGIC; 
  signal SPDB2_OBUF_FBK : STD_LOGIC; 
  signal SPDB2_OBUF_D : STD_LOGIC; 
  signal SPDB2_OBUF_tsimcreated_xor_Q : STD_LOGIC; 
  signal SPDB2_OBUF_RSTF : STD_LOGIC; 
  signal SPDB2_OBUF_tsimcreated_prld_Q : STD_LOGIC; 
  signal SPDB2_OBUF_CLKF : STD_LOGIC; 
  signal SPDB2_OBUF_D1 : STD_LOGIC; 
  signal SPDB2_OBUF_D2 : STD_LOGIC; 
  signal SPDB2_OBUF_D2_PT_0 : STD_LOGIC; 
  signal SPDB2_OBUF_D2_PT_1 : STD_LOGIC; 
  signal D_0_IOBUFE_Q : STD_LOGIC; 
  signal D_0_IOBUFE_BUFOE_OUT : STD_LOGIC; 
  signal D_0_IOBUFE_TRST : STD_LOGIC; 
  signal D_0_IOBUFE_D : STD_LOGIC;