📄 count4.rpt
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cpldfit: version G.35 Xilinx Inc.
Fitter Report
Design Name: count4 Date: 4-25-2006, 2:48PM
Device Used: XC9572-10-TQ100
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
4 /72 ( 6%) 16 /360 ( 4%) 4 /72 ( 6%) 9 /72 ( 12%) 24 /144 ( 17%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 5 5 | I/O : 9 57
Output : 4 4 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 9 9
MACROCELL RESOURCES:
Total Macrocells Available 72
Registered Macrocells 4
Non-registered Macrocell driving I/O 0
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 4 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 4 macrocells used (MC).
End of Resource Summary
*************** Summary of Required Resources ******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
Qout<0> 4 5 FB1_2 STD SLOW 13 I/O O RESET
Qout<1> 4 6 FB3_2 STD SLOW 32 I/O O RESET
Qout<2> 4 7 FB2_2 STD SLOW 94 I/O O RESET
Qout<3> 4 6 FB4_2 STD SLOW 64 I/O O RESET
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
CCLK FB1_8 17 I/O I
CE FB4_11 74 I/O I
CLR FB2_5 95 I/O I
UP<0> FB2_15 11 I/O I
UP<1> FB2_8 97 I/O I
End of Resources
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 1 5 5 4 1/0 18
FB2 1 7 7 4 1/0 18
FB3 1 6 6 4 1/0 18
FB4 1 6 6 4 1/0 18
---- ----- ----- -----
4 16 4/0 72
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 5/31
Number of signals used by logic mapping into function block: 5
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 16 I/O
Qout<0> 4 0 0 1 FB1_2 STD 13 I/O O
(unused) 0 0 0 5 FB1_3 18 I/O
(unused) 0 0 0 5 FB1_4 20 I/O
(unused) 0 0 0 5 FB1_5 14 I/O
(unused) 0 0 0 5 FB1_6 15 I/O
(unused) 0 0 0 5 FB1_7 25 I/O
(unused) 0 0 0 5 FB1_8 17 I/O I
(unused) 0 0 0 5 FB1_9 22 GCK/I/O
(unused) 0 0 0 5 FB1_10 28 I/O
(unused) 0 0 0 5 FB1_11 23 GCK/I/O
(unused) 0 0 0 5 FB1_12 33 I/O
(unused) 0 0 0 5 FB1_13 36 I/O
(unused) 0 0 0 5 FB1_14 27 GCK/I/O
(unused) 0 0 0 5 FB1_15 29 I/O
(unused) 0 0 0 5 FB1_16 39 I/O
(unused) 0 0 0 5 FB1_17 30 I/O
(unused) 0 0 0 5 FB1_18 40 I/O
Signals Used by Logic in Function Block
1: CCLK 3: CLR 5: UP<1>
2: CE 4: UP<0>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
Qout<0> XXXXX................................... 5 5
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 7/29
Number of signals used by logic mapping into function block: 7
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 87 I/O
Qout<2> 4 0 0 1 FB2_2 STD 94 I/O O
(unused) 0 0 0 5 FB2_3 91 I/O
(unused) 0 0 0 5 FB2_4 93 I/O
(unused) 0 0 0 5 FB2_5 95 I/O I
(unused) 0 0 0 5 FB2_6 96 I/O
(unused) 0 0 0 5 FB2_7 3 GTS/I/O
(unused) 0 0 0 5 FB2_8 97 I/O I
(unused) 0 0 0 5 FB2_9 99 GSR/I/O
(unused) 0 0 0 5 FB2_10 1 I/O
(unused) 0 0 0 5 FB2_11 4 GTS/I/O
(unused) 0 0 0 5 FB2_12 6 I/O
(unused) 0 0 0 5 FB2_13 8 I/O
(unused) 0 0 0 5 FB2_14 9 I/O
(unused) 0 0 0 5 FB2_15 11 I/O I
(unused) 0 0 0 5 FB2_16 10 I/O
(unused) 0 0 0 5 FB2_17 12 I/O
(unused) 0 0 0 5 FB2_18 92 I/O
Signals Used by Logic in Function Block
1: CCLK 4: Qout<0> 6: UP<0>
2: CE 5: Qout<1> 7: UP<1>
3: CLR
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
Qout<2> XXXXXXX................................. 7 7
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 6/30
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 41 I/O
Qout<1> 4 0 0 1 FB3_2 STD 32 I/O O
(unused) 0 0 0 5 FB3_3 49 I/O
(unused) 0 0 0 5 FB3_4 50 I/O
(unused) 0 0 0 5 FB3_5 35 I/O
(unused) 0 0 0 5 FB3_6 53 I/O
(unused) 0 0 0 5 FB3_7 54 I/O
(unused) 0 0 0 5 FB3_8 37 I/O
(unused) 0 0 0 5 FB3_9 42 I/O
(unused) 0 0 0 5 FB3_10 60 I/O
(unused) 0 0 0 5 FB3_11 52 I/O
(unused) 0 0 0 5 FB3_12 61 I/O
(unused) 0 0 0 5 FB3_13 63 I/O
(unused) 0 0 0 5 FB3_14 55 I/O
(unused) 0 0 0 5 FB3_15 56 I/O
(unused) 0 0 0 5 FB3_16 65 I/O
(unused) 0 0 0 5 FB3_17 58 I/O
(unused) 0 0 0 5 FB3_18 59 I/O
Signals Used by Logic in Function Block
1: CCLK 3: CLR 5: UP<0>
2: CE 4: Qout<0> 6: UP<1>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
Qout<1> XXXXXX.................................. 6 6
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
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