selwave.ant

xilinx xc9572 cpld 实现的伺服电机控制器

-- D:\FPGA\XC_9572
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Tue Apr 25 16:03:10 2006

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY selwave IS
END selwave;

ARCHITECTURE testbench_arch OF selwave IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "d:\fpga\xc_9572\selwave.ano";
	COMPONENT sel4_1
		PORT (
			A0 : In  std_logic;
			A1 : In  std_logic;
			CS : In  std_logic;
			MR_0 : In  std_logic_vector (7 DOWNTO 0);
			MR_1 : In  std_logic_vector (7 DOWNTO 0);
			MR_2 : In  std_logic_vector (7 DOWNTO 0);
			MR_3 : In  std_logic_vector (7 DOWNTO 0);
			DO : Out  std_logic_vector (7 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL A0 : std_logic;
	SIGNAL A1 : std_logic;
	SIGNAL CS : std_logic;
	SIGNAL MR_0 : std_logic_vector (7 DOWNTO 0);
	SIGNAL MR_1 : std_logic_vector (7 DOWNTO 0);
	SIGNAL MR_2 : std_logic_vector (7 DOWNTO 0);
	SIGNAL MR_3 : std_logic_vector (7 DOWNTO 0);
	SIGNAL DO : std_logic_vector (7 DOWNTO 0);

BEGIN
	UUT : sel4_1
	PORT MAP (
		A0 => A0,
		A1 => A1,
		CS => CS,
		MR_0 => MR_0,
		MR_1 => MR_1,
		MR_2 => MR_2,
		MR_3 => MR_3,
		DO => DO
	);

	PROCESS -- Annotate outputs process
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_DO(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",DO,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DO);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CHECK_LOOP : LOOP
		WAIT FOR 50 ns;
		TX_TIME := TX_TIME + 50;
		ANNOTATE_DO(TX_TIME);
		WAIT FOR 50 ns;
		TX_TIME := TX_TIME + 50;
		END LOOP CHECK_LOOP;
	END PROCESS;

	PROCESS
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		A0 <= transport '0';
		A1 <= transport '0';
		CS <= transport '1';
		MR_0 <= transport std_logic_vector'("00000000"); --0
		MR_1 <= transport std_logic_vector'("00000000"); --0
		MR_2 <= transport std_logic_vector'("00000000"); --0
		MR_3 <= transport std_logic_vector'("00000000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		A0 <= transport '1';
		MR_0 <= transport std_logic_vector'("00110111"); --37
		MR_1 <= transport std_logic_vector'("01000010"); --42
		MR_2 <= transport std_logic_vector'("01001101"); --4D
		MR_3 <= transport std_logic_vector'("00100001"); --21
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		A0 <= transport '0';
		A1 <= transport '1';
		MR_0 <= transport std_logic_vector'("00110111"); --37
		MR_1 <= transport std_logic_vector'("01000010"); --42
		MR_2 <= transport std_logic_vector'("01001101"); --4D
		MR_3 <= transport std_logic_vector'("00100001"); --21
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		A0 <= transport '1';
		CS <= transport '0';
		MR_0 <= transport std_logic_vector'("00110111"); --37
		MR_1 <= transport std_logic_vector'("01000010"); --42
		MR_2 <= transport std_logic_vector'("01001101"); --4D
		MR_3 <= transport std_logic_vector'("00100001"); --21
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		A0 <= transport '0';
		A1 <= transport '0';
		MR_0 <= transport std_logic_vector'("00110111"); --37
		MR_1 <= transport std_logic_vector'("01000010"); --42
		MR_2 <= transport std_logic_vector'("01001101"); --4D
		MR_3 <= transport std_logic_vector'("00100001"); --21
		-- --------------------
		WAIT FOR 100 ns; -- Time=500 ns
		A0 <= transport '1';
		MR_0 <= transport std_logic_vector'("00110111"); --37
		MR_1 <= transport std_logic_vector'("01000010"); --42
		MR_2 <= transport std_logic_vector'("01001101"); --4D
		MR_3 <= transport std_logic_vector'("00100001"); --21
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		A0 <= transport '0';
		A1 <= transport '1';
		MR_0 <= transport std_logic_vector'("00110111"); --37
		MR_1 <= transport std_logic_vector'("01000010"); --42
		MR_2 <= transport std_logic_vector'("01001101"); --4D
		MR_3 <= transport std_logic_vector'("00100001"); --21
		-- --------------------
		WAIT FOR 100 ns; -- Time=700 ns
		A0 <= transport '1';
		MR_0 <= transport std_logic_vector'("00110111"); --37
		MR_1 <= transport std_logic_vector'("01000010"); --42
		MR_2 <= transport std_logic_vector'("01001101"); --4D
		MR_3 <= transport std_logic_vector'("00100001"); --21
		-- --------------------
		WAIT FOR 100 ns; -- Time=800 ns
		A0 <= transport '0';
		A1 <= transport '0';
		MR_0 <= transport std_logic_vector'("00110111"); --37
		MR_1 <= transport std_logic_vector'("01000010"); --42
		MR_2 <= transport std_logic_vector'("01001101"); --4D
		MR_3 <= transport std_logic_vector'("00100001"); --21
		-- --------------------
		WAIT FOR 100 ns; -- Time=900 ns
		A0 <= transport '1';
		MR_0 <= transport std_logic_vector'("00110111"); --37
		MR_1 <= transport std_logic_vector'("01000010"); --42
		MR_2 <= transport std_logic_vector'("01001101"); --4D
		MR_3 <= transport std_logic_vector'("00100001"); --21
		-- --------------------
		WAIT FOR 100 ns; -- Time=1000 ns
		A0 <= transport '0';
		A1 <= transport '1';
		CS <= transport '1';
		MR_0 <= transport std_logic_vector'("00110111"); --37
		MR_1 <= transport std_logic_vector'("01000010"); --42
		MR_2 <= transport std_logic_vector'("01001101"); --4D
		MR_3 <= transport std_logic_vector'("00100001"); --21
		-- --------------------
		WAIT FOR 100 ns; -- Time=1100 ns
		A0 <= transport '1';
		MR_0 <= transport std_logic_vector'("00110111"); --37
		MR_1 <= transport std_logic_vector'("01000010"); --42
		MR_2 <= transport std_logic_vector'("01001101"); --4D
		MR_3 <= transport std_logic_vector'("00100001"); --21
		-- --------------------
		WAIT FOR 100 ns; -- Time=1200 ns
		A0 <= transport '0';
		A1 <= transport '0';
		MR_0 <= transport std_logic_vector'("00110111"); --37
		MR_1 <= transport std_logic_vector'("01000010"); --42
		MR_2 <= transport std_logic_vector'("01001101"); --4D
		-- --------------------
		WAIT FOR 100 ns; -- Time=1300 ns
		A0 <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1400 ns
		A0 <= transport '0';
		A1 <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1500 ns
		A0 <= transport '1';
		-- --------------------
		WAIT FOR 450 ns; -- Time=1950 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION sel4_1_cfg OF selwave IS
	FOR testbench_arch
	END FOR;
END sel4_1_cfg;