mdecode.pnx

xilinx xc9572 cpld 实现的伺服电机控制器

<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ibis [
<!ELEMENT ibis (part, pin+)>
<!ELEMENT part EMPTY>
<!ELEMENT pin EMPTY>
<!ATTLIST part
  arch   CDATA #REQUIRED
  device CDATA #REQUIRED
  spg    CDATA #REQUIRED
  pkg    CDATA #REQUIRED>
<!ATTLIST pin
  nm     CDATA #REQUIRED
  no     CDATA #REQUIRED
  iostd  (TTL|LVTTL|LVCMOS2|NA) "NA"
  sr     (SLOW|FAST|slow|fast) "SLOW"
  dir    (BIDIR|bidir|INPUT|input|OUTPUT|output) "BIDIR">
]>
<ibis><part pkg="TQ100" spg="-10" arch="xc9500" device="XC9572"/><pin nm="CLR1" no="14" dir="input"/><pin nm="MA1" no="95" dir="input"/><pin nm="MB1" no="56" dir="input"/><pin nm="CLR0" no="68" dir="input"/><pin nm="MA0" no="11" dir="input"/><pin nm="MB0" no="74" dir="input"/><pin nm="MC0" no="17" dir="input"/><pin nm="MC1" no="29" dir="input"/><pin nm="RD" no="97" dir="input"/><pin nm="O&lt;0&gt;" no="32" sr="slow" dir="output"/><pin nm="O&lt;1&gt;" no="64" sr="slow" dir="output"/><pin nm="O&lt;2&gt;" no="94" sr="slow" dir="output"/><pin nm="O&lt;3&gt;" no="6" sr="slow" dir="output"/><pin nm="O&lt;4&gt;" no="60" sr="slow" dir="output"/><pin nm="O&lt;5&gt;" no="13" sr="slow" dir="output"/><pin nm="O&lt;6&gt;" no="81" sr="slow" dir="output"/><pin nm="O&lt;7&gt;" no="28" sr="slow" dir="output"/></ibis>