top_timesim.nlf

xilinx xc9572 cpld 实现的伺服电机控制器

Release 6.3i - netgen G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Reading design top.nga ...
  Flattening design ...
  Flattening design completed.
  Specializing design ...
  Specializing design completed.
  Preping physical only global signals ...
  Preping design's networks ...
  Preping design's macros ...
Writing VHDL netlist top_timesim.vhd ...
Writing VHDL SDF file top_timesim.sdf ...
Total memory usage is 38116 kilobytes