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VERSION 6
BEGIN SCHEMATIC
BEGIN ATTR DeviceFamilyName "xc9500"
DELETE all:0
EDITNAME all:0
EDITTRAIT all:0
END ATTR
BEGIN NETLIST
SIGNAL CS4
SIGNAL CSA1
SIGNAL CSA2
SIGNAL MR_0(7:0)
SIGNAL MR_1(7:0)
SIGNAL CS1
SIGNAL A0
SIGNAL A1
SIGNAL A2
SIGNAL CS
SIGNAL SEN0
SIGNAL REL0
SIGNAL M1PS
SIGNAL M1CLR
SIGNAL SEN1
SIGNAL PC1ON
SIGNAL SPDA1
SIGNAL SPDB1
SIGNAL M2PS
SIGNAL M2SG
SIGNAL M2CLR
SIGNAL SEN2
SIGNAL SPDB2
SIGNAL PC2ON
SIGNAL WR
SIGNAL RESET
SIGNAL SPD2A
SIGNAL M1SG
SIGNAL CS3
SIGNAL CS2
SIGNAL CS_U
SIGNAL MR_2(7:0)
SIGNAL MR_0(0)
SIGNAL MR_0(1)
SIGNAL MR_0(2)
SIGNAL MR_0(3)
SIGNAL MR_0(4)
SIGNAL MR_0(5)
SIGNAL MR_0(6)
SIGNAL MR_0(7)
SIGNAL MR_1(3)
SIGNAL MR_1(4)
SIGNAL MR_1(5)
SIGNAL MR_1(6)
SIGNAL MR_1(7)
SIGNAL MR_2(3)
SIGNAL MR_2(4)
SIGNAL MR_2(5)
SIGNAL MR_2(6)
SIGNAL MR_2(7)
SIGNAL MR_1(2)
SIGNAL MR_1(1)
SIGNAL MR_1(0)
SIGNAL MR_2(1)
SIGNAL MR_2(0)
SIGNAL UART0
SIGNAL INT_L0
SIGNAL CLK8
SIGNAL ALMR
SIGNAL INT0
SIGNAL CLK
SIGNAL MR_2(2)
SIGNAL MC0
SIGNAL MB0
SIGNAL MA0
SIGNAL CLR1
SIGNAL NC4
SIGNAL NC3
SIGNAL MC1
SIGNAL MB1
SIGNAL MA1
SIGNAL XLXN_8(7:0)
SIGNAL D(7:0)
SIGNAL CLR0
SIGNAL NC23
SIGNAL RD
PORT Output CS1
PORT Input A0
PORT Input A1
PORT Input A2
PORT Input CS
PORT Output SEN0
PORT Output REL0
PORT Output M1PS
PORT Output M1CLR
PORT Output SEN1
PORT Output PC1ON
PORT Output SPDA1
PORT Output SPDB1
PORT Output M2PS
PORT Output M2SG
PORT Output M2CLR
PORT Output SEN2
PORT Output SPDB2
PORT Output PC2ON
PORT Input WR
PORT Input RESET
PORT Output SPD2A
PORT Output M1SG
PORT Input MR_0(0)
PORT Input MR_0(1)
PORT Input MR_0(2)
PORT Input MR_0(3)
PORT Input MR_0(4)
PORT Input MR_0(5)
PORT Input MR_0(6)
PORT Input MR_0(7)
PORT Input MR_1(3)
PORT Input MR_1(4)
PORT Input MR_1(5)
PORT Input MR_1(6)
PORT Input MR_1(7)
PORT Input MR_2(3)
PORT Input MR_2(4)
PORT Input MR_2(5)
PORT Input MR_2(6)
PORT Input MR_2(7)
PORT Input MR_1(2)
PORT Input MR_1(1)
PORT Input MR_1(0)
PORT Input MR_2(1)
PORT Input MR_2(0)
PORT Output UART0
PORT Input INT_L0
PORT Input CLK8
PORT Output ALMR
PORT Output INT0
PORT Output CLK
PORT Input MR_2(2)
PORT Input MC0
PORT Input MB0
PORT Input MA0
PORT Input MC1
PORT Input MB1
PORT Input MA1
PORT BiDirectional D(7:0)
PORT Input RD
BEGIN BLOCKDEF dq024
TIMESTAMP 2006 4 4 2 20 19
LINE N 416 -192 480 -192
RECTANGLE N 160 -412 416 248
LINE N 480 -384 416 -384
LINE N 416 -352 480 -352
LINE N 416 -320 480 -320
LINE N 416 -288 480 -288
LINE N 480 -256 416 -256
LINE N 416 -224 480 -224
LINE N 160 -128 96 -128
LINE N 96 -96 160 -96
LINE N 96 -64 160 -64
LINE N 416 64 480 64
LINE N 416 96 480 96
LINE N 416 32 480 32
LINE N 480 0 416 0
LINE N 416 -32 480 -32
LINE N 416 -64 480 -64
LINE N 416 -96 480 -96
LINE N 416 -160 480 -160
LINE N 480 -128 416 -128
LINE N 480 128 416 128
LINE N 416 160 480 160
LINE N 416 192 480 192
LINE N 416 224 480 224
LINE N 160 16 96 16
LINE N 96 48 160 48
LINE N 96 80 160 80
LINE N 96 112 160 112
LINE N 160 -256 96 -256
LINE N 96 -256 96 -224
LINE N 96 -224 160 -224
LINE N 160 -240 96 -240
END BLOCKDEF
BEGIN BLOCKDEF logic
TIMESTAMP 2006 3 31 0 55 18
RECTANGLE N 224 160 368 444
LINE N 368 176 416 176
LINE N 176 176 224 176
LINE N 368 208 416 208
LINE N 368 240 416 240
LINE N 368 272 416 272
LINE N 368 304 416 304
LINE N 368 336 416 336
LINE N 368 368 416 368
LINE N 368 400 416 400
LINE N 176 240 224 240
LINE N 176 272 224 272
LINE N 176 304 224 304
LINE N 176 336 224 336
LINE N 176 368 224 368
LINE N 176 208 224 208
END BLOCKDEF
BEGIN BLOCKDEF mdecode
TIMESTAMP 2006 4 25 2 37 2
LINE N 240 496 192 496
LINE N 240 528 192 528
LINE N 240 400 192 400
LINE N 240 432 192 432
LINE N 240 464 192 464
LINE N 192 176 240 176
LINE N 192 208 240 208
LINE N 192 240 240 240
LINE N 192 368 240 368
LINE N 400 224 448 224
LINE N 400 208 448 208
LINE N 448 208 448 240
LINE N 448 240 400 240
RECTANGLE N 240 152 400 564
END BLOCKDEF
BEGIN BLOCKDEF sel4_1
TIMESTAMP 2006 4 6 4 34 27
RECTANGLE N 160 160 368 544
LINE N 368 208 432 208
LINE N 368 272 432 272
LINE N 368 336 432 336
LINE N 368 400 432 400
LINE N 368 480 432 480
LINE N 368 512 432 512
LINE N 160 304 112 304
LINE N 368 448 432 448
LINE N 368 192 432 192
LINE N 432 192 432 224
LINE N 432 224 368 224
LINE N 368 256 432 256
LINE N 432 256 432 288
LINE N 432 288 368 288
LINE N 368 320 432 320
LINE N 432 320 432 352
LINE N 432 352 368 352
LINE N 368 384 432 384
LINE N 432 384 432 412
LINE N 432 412 432 416
LINE N 432 416 368 416
LINE N 160 288 112 288
LINE N 112 288 112 320
LINE N 112 320 160 320
END BLOCKDEF
BEGIN BLOCKDEF decode
TIMESTAMP 2006 4 6 4 54 7
RECTANGLE N 64 -256 320 0
LINE N 64 -224 0 -224
LINE N 64 -160 0 -160
LINE N 64 -96 0 -96
LINE N 64 -32 0 -32
LINE N 320 -224 384 -224
LINE N 320 -160 384 -160
LINE N 320 -96 384 -96
LINE N 320 -32 384 -32
END BLOCKDEF
BEGIN BLOCK XLXI_36 dq024
PIN G CS3
PIN REST RESET
PIN WR WR
PIN D(7:0) D(7:0)
PIN DQ0 SEN0
PIN DQ1 CSA1
PIN DQ2 CSA2
PIN DQ3 REL0
PIN DQ4 CS_U
PIN DQ5 CLR0
PIN DQ6 CLR1
PIN DQ7 NC3
PIN DQ8 M1PS
PIN DQ9 M1SG
PIN DQ10 M1CLR
PIN DQ11 SEN1
PIN DQ12 PC1ON
PIN DQ13 SPDA1
PIN DQ14 SPDB1
PIN DQ15 NC4
PIN DQ16 M2PS
PIN DQ17 M2SG
PIN DQ18 M2CLR
PIN DQ19 SEN2
PIN DQ20 PC2ON
PIN DQ21 SPD2A
PIN DQ22 SPDB2
PIN DQ23 NC23
END BLOCK
BEGIN BLOCK XLXI_57 mdecode
PIN MA0 MA0
PIN MB0 MB0
PIN MC0 MC0
PIN MA1 MA1
PIN MB1 MB1
PIN MC1 MC1
PIN RD RD
PIN O(7:0) XLXN_8(7:0)
PIN CLR0 CLR0
PIN CLR1 CLR1
END BLOCK
BEGIN BLOCK XLXI_45 logic
PIN M0UART MR_2(0)
PIN UART0 UART0
PIN M1UART MR_2(1)
PIN M2UART MR_2(2)
PIN ALM0 MR_1(0)
PIN ALM1 MR_1(1)
PIN ALM2 MR_1(2)
PIN INT_L0 INT_L0
PIN CLK8 CLK8
PIN Addr1 CSA1
PIN Addr2 CSA2
PIN CS_U CS_U
PIN ALM_R ALMR
PIN INT0 INT0
PIN CLK CLK
END BLOCK
BEGIN BLOCK XLXI_58 sel4_1
PIN MR_0(7:0) MR_0(7:0)
PIN MR_1(7:0) MR_1(7:0)
PIN MR_2(7:0) MR_2(7:0)
PIN MR_3(7:0) XLXN_8(7:0)
PIN A1 A1
PIN CS CS4
PIN DO(7:0) D(7:0)
PIN A0 A0
END BLOCK
BEGIN BLOCK XLXI_60 decode
PIN A0 A0
PIN A1 A1
PIN A2 A2
PIN E CS
PIN D0 CS1
PIN D1 CS2
PIN D2 CS3
PIN D3 CS4
END BLOCK
END NETLIST
BEGIN SHEET 1 3520 2720
BEGIN BRANCH MR_0(7:0)
WIRE 1840 752 2080 752
WIRE 2080 320 2080 752
WIRE 2080 320 2560 320
WIRE 2560 320 2560 352
WIRE 2560 352 2560 384
WIRE 2560 384 2560 416
WIRE 2560 416 2560 448
WIRE 2560 448 2560 464
WIRE 2560 208 2560 224
WIRE 2560 224 2560 256
WIRE 2560 256 2560 288
WIRE 2560 288 2560 320
END BRANCH
BEGIN BRANCH MR_1(7:0)
WIRE 1840 816 2080 816
WIRE 2080 800 2080 816
WIRE 2080 800 2560 800
WIRE 2560 800 2560 816
WIRE 2560 816 2560 848
WIRE 2560 848 2560 880
WIRE 2560 880 2560 912
WIRE 2560 912 2560 928
WIRE 2560 672 2560 688
WIRE 2560 688 2560 720
WIRE 2560 720 2560 752
WIRE 2560 752 2560 784
WIRE 2560 784 2560 800
END BRANCH
BEGIN BRANCH CS1
WIRE 1024 336 1104 336
END BRANCH
BEGIN BRANCH CS4
WIRE 1024 528 1104 528
BEGIN DISPLAY 1104 528 ATTR Name
ALIGNMENT SOFT-LEFT
END DISPLAY
END BRANCH
BEGIN BRANCH A0
WIRE 560 336 640 336
END BRANCH
BEGIN BRANCH A1
WIRE 560 400 640 400
END BRANCH
BEGIN BRANCH A2
WIRE 560 464 640 464
END BRANCH
BEGIN BRANCH CS
WIRE 560 528 640 528
END BRANCH
IOMARKER 560 336 A0 R180 28
IOMARKER 560 400 A1 R180 28
IOMARKER 560 464 A2 R180 28
IOMARKER 1104 336 CS1 R0 28
BEGIN BRANCH SEN0
WIRE 1024 1744 1104 1744
END BRANCH
BEGIN BRANCH CSA1
WIRE 1024 1776 1104 1776
BEGIN DISPLAY 1104 1776 ATTR Name
ALIGNMENT SOFT-LEFT
END DISPLAY
END BRANCH
BEGIN BRANCH REL0
WIRE 1024 1840 1104 1840
END BRANCH
BEGIN BRANCH M1PS
WIRE 1024 2000 1104 2000
END BRANCH
BEGIN BRANCH M1CLR
WIRE 1024 2064 1104 2064
END BRANCH
BEGIN BRANCH SEN1
WIRE 1024 2096 1104 2096
END BRANCH
BEGIN BRANCH PC1ON
WIRE 1024 2128 1104 2128
END BRANCH
BEGIN BRANCH SPDA1
WIRE 1024 2160 1104 2160
END BRANCH
BEGIN BRANCH SPDB1
WIRE 1024 2192 1104 2192
END BRANCH
BEGIN BRANCH M2PS
WIRE 1024 2256 1104 2256
END BRANCH
BEGIN BRANCH M2SG
WIRE 1024 2288 1104 2288
END BRANCH
BEGIN BRANCH M2CLR
WIRE 1024 2320 1104 2320
END BRANCH
BEGIN BRANCH SEN2
WIRE 1024 2352 1104 2352
END BRANCH
BEGIN BRANCH SPDB2
WIRE 560 2208 640 2208
END BRANCH
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