sel4_1.syr

来自「xilinx xc9572 cpld 实现的伺服电机控制器」· SYR 代码 · 共 155 行

Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: sel4_1.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : sel4_1.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : sel4_1
Output Format                      : NGC
Target Device                      : xc9500

---- Source Options
Top Module Name                    : sel4_1
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Goal                  : Area
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : sel4_1.lso
verilog2001                        : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/FPGA/xc_9572/sel4_1.vhd in Library work.
Architecture behavioral of Entity sel4_1 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sel4_1> (Architecture <behavioral>).
INFO:Xst:1561 - D:/FPGA/xc_9572/sel4_1.vhd line 51: Mux is complete : default of case is discarded
Entity <sel4_1> analyzed. Unit <sel4_1> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <sel4_1>.
    Related source file is D:/FPGA/xc_9572/sel4_1.vhd.
    Found 8-bit tristate buffer for signal <DO>.
    Found 8-bit 4-to-1 multiplexer for signal <$n0001> created at line 47.
    Summary:
	inferred   8 Tristate(s).
Unit <sel4_1> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Multiplexers                     : 1
 8-bit 4-to-1 multiplexer          : 1
# Tristates                        : 1
 8-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <sel4_1> ...

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : sel4_1.ngr
Top Level Output File Name         : sel4_1
Output Format                      : NGC
Optimization Goal                  : Area
Keep Hierarchy                     : YES
Target Technology                  : xc9500
Macro Preserve                     : YES
XOR Preserve                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 43

Macro Statistics :
# Tristates                        : 1
#      8-bit tristate buffer       : 1

Cell Usage :
# BELS                             : 97
#      AND2                        : 48
#      INV                         : 25
#      OR2                         : 24
# IO Buffers                       : 43
#      IBUF                        : 35
#      OBUFE                       : 8
=========================================================================
CPU : 1.64 / 2.66 s | Elapsed : 2.00 / 3.00 s
 
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