📄 decode.rpt
字号:
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 4/32
Number of signals used by logic mapping into function block: 4
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 66 I/O
D2 1 0 0 4 FB4_2 STD 64 I/O O
(unused) 0 0 0 5 FB4_3 71 I/O
(unused) 0 0 0 5 FB4_4 72 I/O
(unused) 0 0 0 5 FB4_5 67 I/O
(unused) 0 0 0 5 FB4_6 76 I/O
(unused) 0 0 0 5 FB4_7 77 I/O
(unused) 0 0 0 5 FB4_8 68 I/O
(unused) 0 0 0 5 FB4_9 70 I/O
(unused) 0 0 0 5 FB4_10 81 I/O
(unused) 0 0 0 5 FB4_11 74 I/O I
(unused) 0 0 0 5 FB4_12 82 I/O
(unused) 0 0 0 5 FB4_13 85 I/O
(unused) 0 0 0 5 FB4_14 78 I/O
(unused) 0 0 0 5 FB4_15 89 I/O
(unused) 0 0 0 5 FB4_16 86 I/O
(unused) 0 0 0 5 FB4_17 90 I/O
(unused) 0 0 0 5 FB4_18 79 I/O
Signals Used by Logic in Function Block
1: A0 3: A2 4: E
2: A1
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
D2 XXXX.................................... 4 4
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
D0 <= NOT ((NOT E AND NOT A2 AND NOT A1 AND NOT A0));
D1 <= NOT ((NOT E AND NOT A2 AND NOT A1 AND A0));
D2 <= NOT ((NOT E AND NOT A2 AND A1 AND NOT A0));
D3 <= NOT ((NOT E AND A2));
Register Legend:
FDCPE (Q,D,C,CLR,PRE);
FTCPE (Q,D,C,CLR,PRE);
LDCP (Q,D,G,CLR,PRE);
**************************** Device Pin Out ****************************
Device : XC9572-10-TQ100
--------------------------------------------------
/100 98 96 94 92 90 88 86 84 82 80 78 76 \
| 99 97 95 93 91 89 87 85 83 81 79 77 |
| 1 75 |
| 2 74 |
| 3 73 |
| 4 72 |
| 5 71 |
| 6 70 |
| 7 69 |
| 8 68 |
| 9 67 |
| 10 66 |
| 11 65 |
| 12 64 |
| 13 XC9572-10-TQ100 63 |
| 14 62 |
| 15 61 |
| 16 60 |
| 17 59 |
| 18 58 |
| 19 57 |
| 20 56 |
| 21 55 |
| 22 54 |
| 23 53 |
| 24 52 |
| 25 51 |
| 27 29 31 33 35 37 39 41 43 45 47 49 |
\26 28 30 32 34 36 38 40 42 44 46 48 50 /
--------------------------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 PGND 51 VCC
2 NC 52 PGND
3 PGND 53 PGND
4 PGND 54 PGND
5 VCC 55 PGND
6 PGND 56 PGND
7 NC 57 VCC
8 PGND 58 PGND
9 PGND 59 PGND
10 PGND 60 PGND
11 A2 61 PGND
12 PGND 62 GND
13 D3 63 PGND
14 PGND 64 D2
15 PGND 65 PGND
16 PGND 66 PGND
17 A0 67 PGND
18 PGND 68 PGND
19 NC 69 GND
20 PGND 70 PGND
21 GND 71 PGND
22 PGND 72 PGND
23 PGND 73 NC
24 NC 74 A1
25 PGND 75 GND
26 VCC 76 PGND
27 PGND 77 PGND
28 PGND 78 PGND
29 PGND 79 PGND
30 PGND 80 NC
31 GND 81 PGND
32 D1 82 PGND
33 PGND 83 TDO
34 NC 84 GND
35 PGND 85 PGND
36 PGND 86 PGND
37 PGND 87 PGND
38 VCC 88 VCC
39 PGND 89 PGND
40 PGND 90 PGND
41 PGND 91 PGND
42 PGND 92 PGND
43 NC 93 PGND
44 GND 94 D0
45 TDI 95 PGND
46 NC 96 PGND
47 TMS 97 E
48 TCK 98 VCC
49 PGND 99 PGND
50 PGND 100 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9572-10-TQ100
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : SLOW
Power Mode : STD
Ground on Unused IOs : ON
Global Clock Optimization : OFF
Global Set/Reset Optimization : OFF
Global Ouput Enable Optimization : OFF
FASTConnect/UIM optimzation : ON
Local Feedback : ON
Pin Feedback : ON
Input Limit : 36
Pterm Limit : 25
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -