top.syr

xilinx xc9572 cpld 实现的伺服电机控制器

Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : top.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : top
Output Format                      : NGC
Target Device                      : xc9500

---- Source Options
Top Module Name                    : top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Goal                  : Area
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : top.lso
verilog2001                        : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/FPGA/xc_9572/count4.vhdl in Library work.
Architecture behavioral of Entity count4 is up to date.
Compiling vhdl file D:/FPGA/xc_9572/d5_32e.vhd in Library work.
Architecture behavioral of Entity d5_32e is up to date.
Compiling vhdl file D:/FPGA/xc_9572/dq24.vhd in Library work.
Architecture behavioral of Entity dq24 is up to date.
Compiling vhdl file D:/FPGA/xc_9572/dq024.vhd in Library work.
Architecture behavioral of Entity dq024 is up to date.
Compiling vhdl file D:/FPGA/xc_9572/logic.vhd in Library work.
Architecture behavioral of Entity logic is up to date.
Compiling vhdl file D:/FPGA/xc_9572/mdecode.vhd in Library work.
Architecture behavioral of Entity mdecode is up to date.
Compiling vhdl file D:/FPGA/xc_9572/sel4_1.vhd in Library work.
Architecture behavioral of Entity sel4_1 is up to date.
Compiling vhdl file D:/FPGA/xc_9572/DECODE.vhd in Library work.
Architecture behavioral of Entity decode is up to date.
Compiling vhdl file D:/FPGA/xc_9572/top.vhf in Library work.
Entity <top> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top> (Architecture <behavioral>).
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <dq024> (Architecture <behavioral>).
Entity <dq024> analyzed. Unit <dq024> generated.

Analyzing Entity <d5_32e> (Architecture <behavioral>).
Entity <d5_32e> analyzed. Unit <d5_32e> generated.

Analyzing Entity <dq24> (Architecture <behavioral>).
Entity <dq24> analyzed. Unit <dq24> generated.

Analyzing Entity <logic> (Architecture <behavioral>).
Entity <logic> analyzed. Unit <logic> generated.

Analyzing Entity <mdecode> (Architecture <behavioral>).
Entity <mdecode> analyzed. Unit <mdecode> generated.

Analyzing Entity <count4> (Architecture <behavioral>).
Entity <count4> analyzed. Unit <count4> generated.

Analyzing Entity <sel4_1> (Architecture <behavioral>).
INFO:Xst:1561 - D:/FPGA/xc_9572/sel4_1.vhd line 51: Mux is complete : default of case is discarded
Entity <sel4_1> analyzed. Unit <sel4_1> generated.

Analyzing Entity <decode> (Architecture <behavioral>).
Entity <decode> analyzed. Unit <decode> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <count4>.
    Related source file is D:/FPGA/xc_9572/count4.vhdl.
    Found 1-bit register for signal <dir>.
    Found 3-bit updown counter for signal <Temp>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <count4> synthesized.


Synthesizing Unit <dq24>.
    Related source file is D:/FPGA/xc_9572/dq24.vhd.
Unit <dq24> synthesized.


Synthesizing Unit <d5_32e>.
    Related source file is D:/FPGA/xc_9572/d5_32e.vhd.
Unit <d5_32e> synthesized.


Synthesizing Unit <decode>.
    Related source file is D:/FPGA/xc_9572/DECODE.vhd.
Unit <decode> synthesized.


Synthesizing Unit <sel4_1>.
    Related source file is D:/FPGA/xc_9572/sel4_1.vhd.
    Found 8-bit tristate buffer for signal <DO>.
    Found 8-bit 4-to-1 multiplexer for signal <$n0001> created at line 47.
    Summary:
	inferred   8 Tristate(s).
Unit <sel4_1> synthesized.


Synthesizing Unit <mdecode>.
    Related source file is D:/FPGA/xc_9572/mdecode.vhd.
WARNING:Xst:737 - Found 8-bit latch for signal <O>.
Unit <mdecode> synthesized.


Synthesizing Unit <logic>.
    Related source file is D:/FPGA/xc_9572/logic.vhd.
Unit <logic> synthesized.


Synthesizing Unit <dq024>.
    Related source file is D:/FPGA/xc_9572/dq024.vhd.
WARNING:Xst:647 - Input <D<6:5>> is never used.
Unit <dq024> synthesized.


Synthesizing Unit <top>.
    Related source file is D:/FPGA/xc_9572/top.vhf.
WARNING:Xst:646 - Signal <CS2> is assigned but never used.
WARNING:Xst:646 - Signal <NC3> is assigned but never used.
WARNING:Xst:646 - Signal <NC4> is assigned but never used.
WARNING:Xst:646 - Signal <NC23> is assigned but never used.
Unit <top> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 2
 3-bit updown counter              : 2
# Registers                        : 2
 1-bit register                    : 2
# Latches                          : 1
 8-bit latch                       : 1
# Multiplexers                     : 1
 8-bit 4-to-1 multiplexer          : 1
# Tristates                        : 1
 8-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1348 - Unit sel4_1 is merged (output interface has tristates)
WARNING:Xst:1355 - Unit logic is merged (low complexity)

Optimizing unit <top> ...

Optimizing unit <decode> ...

Optimizing unit <d5_32e> ...

Optimizing unit <dq24> ...

Optimizing unit <dq024> ...

Optimizing unit <count4> ...

Optimizing unit <mdecode> ...

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : top.ngr
Top Level Output File Name         : top
Output Format                      : NGC
Optimization Goal                  : Area
Keep Hierarchy                     : YES
Target Technology                  : xc9500
Macro Preserve                     : YES
XOR Preserve                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 68

Macro Statistics :
# Registers                        : 8
#      1-bit register              : 8
# Tristates                        : 1
#      8-bit tristate buffer       : 1
# Xors                             : 8
#      1-bit xor2                  : 8

Cell Usage :
# BELS                             : 331
#      AND2                        : 136
#      AND3                        : 7
#      AND4                        : 6
#      GND                         : 1
#      INV                         : 119
#      OR2                         : 50
#      OR3                         : 1
#      OR4                         : 1
#      VCC                         : 2
#      XOR2                        : 8
# FlipFlops/Latches                : 40
#      FDC                         : 8
#      FDCE                        : 24
#      LD                          : 8
# IO Buffers                       : 68
#      IBUF                        : 39
#      IOBUFE                      : 6
#      OBUF                        : 21
#      OBUFE                       : 2
=========================================================================
CPU : 2.30 / 3.22 s | Elapsed : 2.00 / 3.00 s
 
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