📄 sel4_1.rpt
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(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 11/25
Number of signals used by logic mapping into function block: 11
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 66 I/O
(unused) 0 0 0 5 FB4_2 64 I/O I
DO<1> 5 0 0 0 FB4_3 STD 71 I/O O
(unused) 0 0 0 5 FB4_4 72 I/O
(unused) 0 0 0 5 FB4_5 67 I/O I
(unused) 0 0 0 5 FB4_6 76 I/O
(unused) 0 0 0 5 FB4_7 77 I/O I
(unused) 0 0 0 5 FB4_8 68 I/O I
(unused) 0 0 0 5 FB4_9 70 I/O I
DO<4> 5 0 0 0 FB4_10 STD 81 I/O O
(unused) 0 0 0 5 FB4_11 74 I/O I
(unused) 0 0 0 5 FB4_12 82 I/O
(unused) 0 0 0 5 FB4_13 85 I/O
(unused) 0 0 0 5 FB4_14 78 I/O I
(unused) 0 0 0 5 FB4_15 89 I/O I
(unused) 0 0 0 5 FB4_16 86 I/O
(unused) 0 0 0 5 FB4_17 90 I/O I
(unused) 0 0 0 5 FB4_18 79 I/O
Signals Used by Logic in Function Block
1: A0 5: MR_0<4> 9: MR_2<4>
2: A1 6: MR_1<1> 10: MR_3<1>
3: CS 7: MR_1<4> 11: MR_3<4>
4: MR_0<1> 8: MR_2<1>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DO<1> XXXX.X.X.X.............................. 7 7
DO<4> XXX.X.X.X.X............................. 7 7
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
DO_I(0) <= ((A1 AND MR_0(0) AND A0)
OR (A1 AND MR_1(0) AND NOT A0)
OR (NOT A1 AND MR_2(0) AND A0)
OR (NOT A1 AND MR_3(0) AND NOT A0));
DO(0) <= DO_I(0) when DO_OE(0) = '1' else 'Z';
DO_OE(0) <= NOT CS;
DO_I(1) <= ((A1 AND MR_0(1) AND A0)
OR (A1 AND MR_1(1) AND NOT A0)
OR (NOT A1 AND MR_2(1) AND A0)
OR (NOT A1 AND MR_3(1) AND NOT A0));
DO(1) <= DO_I(1) when DO_OE(1) = '1' else 'Z';
DO_OE(1) <= NOT CS;
DO_I(2) <= ((A1 AND MR_0(2) AND A0)
OR (A1 AND MR_1(2) AND NOT A0)
OR (NOT A1 AND MR_2(2) AND A0)
OR (NOT A1 AND MR_3(2) AND NOT A0));
DO(2) <= DO_I(2) when DO_OE(2) = '1' else 'Z';
DO_OE(2) <= NOT CS;
DO_I(3) <= ((A1 AND MR_0(3) AND A0)
OR (A1 AND MR_1(3) AND NOT A0)
OR (NOT A1 AND MR_2(3) AND A0)
OR (NOT A1 AND MR_3(3) AND NOT A0));
DO(3) <= DO_I(3) when DO_OE(3) = '1' else 'Z';
DO_OE(3) <= NOT CS;
DO_I(4) <= ((A1 AND MR_0(4) AND A0)
OR (A1 AND MR_1(4) AND NOT A0)
OR (NOT A1 AND MR_2(4) AND A0)
OR (NOT A1 AND MR_3(4) AND NOT A0));
DO(4) <= DO_I(4) when DO_OE(4) = '1' else 'Z';
DO_OE(4) <= NOT CS;
DO_I(5) <= ((A1 AND MR_0(5) AND A0)
OR (A1 AND MR_1(5) AND NOT A0)
OR (NOT A1 AND MR_2(5) AND A0)
OR (NOT A1 AND MR_3(5) AND NOT A0));
DO(5) <= DO_I(5) when DO_OE(5) = '1' else 'Z';
DO_OE(5) <= NOT CS;
DO_I(6) <= ((MR_0(6) AND A1 AND A0)
OR (A1 AND MR_1(6) AND NOT A0)
OR (NOT A1 AND MR_2(6) AND A0)
OR (NOT A1 AND MR_3(6) AND NOT A0));
DO(6) <= DO_I(6) when DO_OE(6) = '1' else 'Z';
DO_OE(6) <= NOT CS;
DO_I(7) <= ((A1 AND MR_0(7) AND A0)
OR (A1 AND MR_1(7) AND NOT A0)
OR (NOT A1 AND MR_2(7) AND A0)
OR (NOT A1 AND MR_3(7) AND NOT A0));
DO(7) <= DO_I(7) when DO_OE(7) = '1' else 'Z';
DO_OE(7) <= NOT CS;
Register Legend:
FDCPE (Q,D,C,CLR,PRE);
FTCPE (Q,D,C,CLR,PRE);
LDCP (Q,D,G,CLR,PRE);
**************************** Device Pin Out ****************************
Device : XC9572-10-TQ100
--------------------------------------------------
/100 98 96 94 92 90 88 86 84 82 80 78 76 \
| 99 97 95 93 91 89 87 85 83 81 79 77 |
| 1 75 |
| 2 74 |
| 3 73 |
| 4 72 |
| 5 71 |
| 6 70 |
| 7 69 |
| 8 68 |
| 9 67 |
| 10 66 |
| 11 65 |
| 12 64 |
| 13 XC9572-10-TQ100 63 |
| 14 62 |
| 15 61 |
| 16 60 |
| 17 59 |
| 18 58 |
| 19 57 |
| 20 56 |
| 21 55 |
| 22 54 |
| 23 53 |
| 24 52 |
| 25 51 |
| 27 29 31 33 35 37 39 41 43 45 47 49 |
\26 28 30 32 34 36 38 40 42 44 46 48 50 /
--------------------------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 TIE 51 VCC
2 NC 52 MR_0<2>
3 TIE 53 TIE
4 TIE 54 TIE
5 VCC 55 MR_0<1>
6 DO<7> 56 MR_1<6>
7 NC 57 VCC
8 TIE 58 MR_0<0>
9 MR_1<3> 59 TIE
10 TIE 60 DO<3>
11 MR_1<5> 61 MR_0<4>
12 MR_3<7> 62 GND
13 MR_3<2> 63 TIE
14 MR_2<6> 64 MR_3<5>
15 MR_0<3> 65 MR_1<1>
16 MR_3<1> 66 TIE
17 MR_2<5> 67 MR_0<7>
18 DO<5> 68 MR_0<6>
19 NC 69 GND
20 TIE 70 MR_3<3>
21 GND 71 DO<1>
22 TIE 72 TIE
23 TIE 73 NC
24 NC 74 MR_0<5>
25 TIE 75 GND
26 VCC 76 TIE
27 TIE 77 MR_1<4>
28 DO<6> 78 MR_3<0>
29 MR_3<6> 79 TIE
30 MR_2<0> 80 NC
31 GND 81 DO<4>
32 A0 82 TIE
33 MR_2<4> 83 TDO
34 NC 84 GND
35 MR_1<7> 85 TIE
36 TIE 86 TIE
37 MR_2<1> 87 TIE
38 VCC 88 VCC
39 TIE 89 MR_2<7>
40 TIE 90 MR_2<2>
41 TIE 91 DO<2>
42 MR_1<2> 92 TIE
43 NC 93 TIE
44 GND 94 MR_2<3>
45 TDI 95 CS
46 NC 96 MR_1<0>
47 TMS 97 A1
48 TCK 98 VCC
49 DO<0> 99 TIE
50 MR_3<4> 100 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9572-10-TQ100
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : SLOW
Power Mode : AUTO
Ground on Unused IOs : OFF
Global Clock Optimization : OFF
Global Set/Reset Optimization : OFF
Global Ouput Enable Optimization : OFF
FASTConnect/UIM optimzation : ON
Local Feedback : ON
Pin Feedback : ON
Input Limit : 36
Pterm Limit : 25
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