📄 sel4_1.rpt
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cpldfit: version G.35 Xilinx Inc.
Fitter Report
Design Name: sel4_1 Date: 4-25-2006, 4:20PM
Device Used: XC9572-10-TQ100
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
8 /72 ( 11%) 40 /360 ( 11%) 0 /72 ( 0%) 43 /72 ( 60%) 44 /144 ( 31%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 35 35 | I/O : 43 23
Output : 8 8 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 43 43
MACROCELL RESOURCES:
Total Macrocells Available 72
Registered Macrocells 0
Non-registered Macrocell driving I/O 8
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 8 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 8 macrocells used (MC).
End of Resource Summary
*************** Summary of Required Resources ******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
DO<0> 5 7 FB3_3 STD SLOW 49 I/O O
DO<1> 5 7 FB4_3 STD SLOW 71 I/O O
DO<2> 5 7 FB2_3 STD SLOW 91 I/O O
DO<3> 5 7 FB3_10 STD SLOW 60 I/O O
DO<4> 5 7 FB4_10 STD SLOW 81 I/O O
DO<5> 5 7 FB1_3 STD SLOW 18 I/O O
DO<6> 5 7 FB1_10 STD SLOW 28 I/O O
DO<7> 5 7 FB2_12 STD SLOW 6 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
A0 FB3_2 32 I/O I
A1 FB2_8 97 I/O I
CS FB2_5 95 I/O I
MR_0<0> FB3_17 58 I/O I
MR_0<1> FB3_14 55 I/O I
MR_0<2> FB3_11 52 I/O I
MR_0<3> FB1_6 15 I/O I
MR_0<4> FB3_12 61 I/O I
MR_0<5> FB4_11 74 I/O I
MR_0<6> FB4_8 68 I/O I
MR_0<7> FB4_5 67 I/O I
MR_1<0> FB2_6 96 I/O I
MR_1<1> FB3_16 65 I/O I
MR_1<2> FB3_9 42 I/O I
MR_1<3> FB2_14 9 I/O I
MR_1<4> FB4_7 77 I/O I
MR_1<5> FB2_15 11 I/O I
MR_1<6> FB3_15 56 I/O I
MR_1<7> FB3_5 35 I/O I
MR_2<0> FB1_17 30 I/O I
MR_2<1> FB3_8 37 I/O I
MR_2<2> FB4_17 90 I/O I
MR_2<3> FB2_2 94 I/O I
MR_2<4> FB1_12 33 I/O I
MR_2<5> FB1_8 17 I/O I
MR_2<6> FB1_5 14 I/O I
MR_2<7> FB4_15 89 I/O I
MR_3<0> FB4_14 78 I/O I
MR_3<1> FB1_1 16 I/O I
MR_3<2> FB1_2 13 I/O I
MR_3<3> FB4_9 70 I/O I
MR_3<4> FB3_4 50 I/O I
MR_3<5> FB4_2 64 I/O I
MR_3<6> FB1_15 29 I/O I
MR_3<7> FB2_17 12 I/O I
End of Resources
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 2 11 11 10 2/0 18
FB2 2 11 11 10 2/0 18
FB3 2 11 11 10 2/0 18
FB4 2 11 11 10 2/0 18
---- ----- ----- -----
8 40 8/0 72
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 11/25
Number of signals used by logic mapping into function block: 11
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 16 I/O I
(unused) 0 0 0 5 FB1_2 13 I/O I
DO<5> 5 0 0 0 FB1_3 STD 18 I/O O
(unused) 0 0 0 5 FB1_4 20 I/O
(unused) 0 0 0 5 FB1_5 14 I/O I
(unused) 0 0 0 5 FB1_6 15 I/O I
(unused) 0 0 0 5 FB1_7 25 I/O
(unused) 0 0 0 5 FB1_8 17 I/O I
(unused) 0 0 0 5 FB1_9 22 GCK/I/O
DO<6> 5 0 0 0 FB1_10 STD 28 I/O O
(unused) 0 0 0 5 FB1_11 23 GCK/I/O
(unused) 0 0 0 5 FB1_12 33 I/O I
(unused) 0 0 0 5 FB1_13 36 I/O
(unused) 0 0 0 5 FB1_14 27 GCK/I/O
(unused) 0 0 0 5 FB1_15 29 I/O I
(unused) 0 0 0 5 FB1_16 39 I/O
(unused) 0 0 0 5 FB1_17 30 I/O I
(unused) 0 0 0 5 FB1_18 40 I/O
Signals Used by Logic in Function Block
1: A0 5: MR_0<6> 9: MR_2<6>
2: A1 6: MR_1<5> 10: MR_3<5>
3: CS 7: MR_1<6> 11: MR_3<6>
4: MR_0<5> 8: MR_2<5>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DO<5> XXXX.X.X.X.............................. 7 7
DO<6> XXX.X.X.X.X............................. 7 7
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 11/25
Number of signals used by logic mapping into function block: 11
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 87 I/O
(unused) 0 0 0 5 FB2_2 94 I/O I
DO<2> 5 0 0 0 FB2_3 STD 91 I/O O
(unused) 0 0 0 5 FB2_4 93 I/O
(unused) 0 0 0 5 FB2_5 95 I/O I
(unused) 0 0 0 5 FB2_6 96 I/O I
(unused) 0 0 0 5 FB2_7 3 GTS/I/O
(unused) 0 0 0 5 FB2_8 97 I/O I
(unused) 0 0 0 5 FB2_9 99 GSR/I/O
(unused) 0 0 0 5 FB2_10 1 I/O
(unused) 0 0 0 5 FB2_11 4 GTS/I/O
DO<7> 5 0 0 0 FB2_12 STD 6 I/O O
(unused) 0 0 0 5 FB2_13 8 I/O
(unused) 0 0 0 5 FB2_14 9 I/O I
(unused) 0 0 0 5 FB2_15 11 I/O I
(unused) 0 0 0 5 FB2_16 10 I/O
(unused) 0 0 0 5 FB2_17 12 I/O I
(unused) 0 0 0 5 FB2_18 92 I/O
Signals Used by Logic in Function Block
1: A0 5: MR_0<7> 9: MR_2<7>
2: A1 6: MR_1<2> 10: MR_3<2>
3: CS 7: MR_1<7> 11: MR_3<7>
4: MR_0<2> 8: MR_2<2>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DO<2> XXXX.X.X.X.............................. 7 7
DO<7> XXX.X.X.X.X............................. 7 7
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 11/25
Number of signals used by logic mapping into function block: 11
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 41 I/O
(unused) 0 0 0 5 FB3_2 32 I/O I
DO<0> 5 0 0 0 FB3_3 STD 49 I/O O
(unused) 0 0 0 5 FB3_4 50 I/O I
(unused) 0 0 0 5 FB3_5 35 I/O I
(unused) 0 0 0 5 FB3_6 53 I/O
(unused) 0 0 0 5 FB3_7 54 I/O
(unused) 0 0 0 5 FB3_8 37 I/O I
(unused) 0 0 0 5 FB3_9 42 I/O I
DO<3> 5 0 0 0 FB3_10 STD 60 I/O O
(unused) 0 0 0 5 FB3_11 52 I/O I
(unused) 0 0 0 5 FB3_12 61 I/O I
(unused) 0 0 0 5 FB3_13 63 I/O
(unused) 0 0 0 5 FB3_14 55 I/O I
(unused) 0 0 0 5 FB3_15 56 I/O I
(unused) 0 0 0 5 FB3_16 65 I/O I
(unused) 0 0 0 5 FB3_17 58 I/O I
(unused) 0 0 0 5 FB3_18 59 I/O
Signals Used by Logic in Function Block
1: A0 5: MR_0<3> 9: MR_2<3>
2: A1 6: MR_1<0> 10: MR_3<0>
3: CS 7: MR_1<3> 11: MR_3<3>
4: MR_0<0> 8: MR_2<0>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DO<0> XXXX.X.X.X.............................. 7 7
DO<3> XXX.X.X.X.X............................. 7 7
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
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