copy_of_d3_8e.vhd

xilinx xc9572 cpld 实现的伺服电机控制器

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-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 6.3i
--  \   \         Application : 
--  /   /         Filename : xil_1076_6
-- /___/   /\     Timestamp : 04/03/2006 09:18:31
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: copy_of_d3_8e
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity copy_of_d3_8e is
   port ( A0 : in    std_logic; 
          A1 : in    std_logic; 
          A2 : in    std_logic; 
          E  : in    std_logic; 
          D0 : out   std_logic; 
          D1 : out   std_logic; 
          D2 : out   std_logic; 
          D3 : out   std_logic; 
          D4 : out   std_logic; 
          D5 : out   std_logic; 
          D6 : out   std_logic; 
          D7 : out   std_logic);
end copy_of_d3_8e;

architecture BEHAVIORAL of copy_of_d3_8e is
begin
end BEHAVIORAL;

-- synopsys translate_off
configuration CFG_copy_of_d3_8e of  copy_of_d3_8e is
   for BEHAVIORAL
   end for;
end CFG_copy_of_d3_8e;
-- synopsys translate_on