📄 top.rpt
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# !_LC1_B3 & _LC1_B6;
-- Node name is '|urat:1|js_tb:93|jsck4' from file "js_tb.tdf" line 8, column 6
-- Equation name is '_LC8_B2', type is buried
_LC8_B2 = DFFE( _EQ026, !_LC3_C17, !_LC3_B2, VCC, VCC);
_EQ026 = !_LC1_B6 & _LC8_B2
# !_LC2_B3 & _LC8_B2
# _LC1_B3 & _LC1_B6 & _LC2_B3 & !_LC8_B2
# !_LC1_B3 & _LC8_B2;
-- Node name is '|urat:1|js_tb:93|jsck5' from file "js_tb.tdf" line 8, column 6
-- Equation name is '_LC2_B2', type is buried
_LC2_B2 = DFFE( _EQ027, !_LC3_C17, !_LC3_B2, VCC, VCC);
_EQ027 = !_LC1_B2 & _LC1_B3 & _LC2_B2
# _LC1_B2 & _LC1_B3 & !_LC2_B2
# _LC3_B3;
-- Node name is '|urat:1|js_tb:93|jsck6' from file "js_tb.tdf" line 8, column 6
-- Equation name is '_LC4_B3', type is buried
_LC4_B3 = DFFE( _EQ028, !_LC3_C17, !_LC3_B2, VCC, VCC);
_EQ028 = !_LC2_B2 & _LC4_B3
# !_LC1_B2 & _LC4_B3
# _LC1_B2 & _LC2_B2 & !_LC4_B3 & !_LC8_B3
# _LC4_B3 & _LC8_B3;
-- Node name is '|urat:1|js_tb:93|jsck7' from file "js_tb.tdf" line 8, column 6
-- Equation name is '_LC8_B3', type is buried
_LC8_B3 = DFFE( _EQ029, !_LC3_C17, !_LC3_B2, VCC, VCC);
_EQ029 = _LC8_B3
# _LC1_B2 & _LC2_B2 & _LC4_B3;
-- Node name is '|urat:1|js_tb:93|:54' from file "js_tb.tdf" line 14, column 16
-- Equation name is '_LC1_B3', type is buried
!_LC1_B3 = _LC1_B3~NOT;
_LC1_B3~NOT = LCELL( _EQ030);
_EQ030 = _LC4_B3 & _LC8_B3
# _LC2_B2 & _LC8_B3;
-- Node name is '|urat:1|js_tb:93|:65' from file "js_tb.tdf" line 15, column 21
-- Equation name is '_LC2_B3', type is buried
_LC2_B3 = LCELL( _EQ031);
_EQ031 = _LC5_B3 & _LC6_B3 & _LC7_B3;
-- Node name is '|urat:1|js_tb:93|:73' from file "js_tb.tdf" line 15, column 21
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = LCELL( _EQ032);
_EQ032 = _LC1_B6 & _LC2_B3 & _LC8_B2;
-- Node name is '|urat:1|js_tb:93|:110' from file "js_tb.tdf" line 17, column 12
-- Equation name is '_LC3_B3', type is buried
_LC3_B3 = LCELL( _EQ033);
_EQ033 = _LC2_B2 & _LC8_B3;
-- Node name is '|urat:1|js_tb:93|:122' from file "js_tb.tdf" line 20, column 20
-- Equation name is '_LC4_B2', type is buried
!_LC4_B2 = _LC4_B2~NOT;
_LC4_B2~NOT = LCELL( _EQ034);
_EQ034 = _LC3_B3 & !_LC4_B3 & !_LC8_B2;
-- Node name is '|urat:1|m16:25|fp0' from file "m16.tdf" line 8, column 4
-- Equation name is '_LC5_B19', type is buried
_LC5_B19 = DFFE(!_LC5_B19, !_LC3_C17, VCC, VCC, VCC);
-- Node name is '|urat:1|m16:25|fp1' from file "m16.tdf" line 8, column 4
-- Equation name is '_LC6_B19', type is buried
_LC6_B19 = DFFE( _EQ035, !_LC3_C17, VCC, VCC, VCC);
_EQ035 = _LC5_B19 & !_LC6_B19
# !_LC5_B19 & _LC6_B19;
-- Node name is '|urat:1|m16:25|fp2' from file "m16.tdf" line 8, column 4
-- Equation name is '_LC7_B19', type is buried
_LC7_B19 = DFFE( _EQ036, !_LC3_C17, VCC, VCC, VCC);
_EQ036 = !_LC5_B19 & _LC7_B19
# !_LC6_B19 & _LC7_B19
# _LC5_B19 & _LC6_B19 & !_LC7_B19;
-- Node name is '|urat:1|m16:25|fp3' from file "m16.tdf" line 8, column 4
-- Equation name is '_LC4_B19', type is buried
_LC4_B19 = DFFE( _EQ037, !_LC3_C17, VCC, VCC, VCC);
_EQ037 = _LC4_B19 & !_LC5_B19
# _LC4_B19 & !_LC6_B19
# _LC4_B19 & !_LC7_B19
# !_LC4_B19 & _LC5_B19 & _LC6_B19 & _LC7_B19;
-- Node name is '|urat:1|s_clk:40|fp0' from file "s_clk.tdf" line 8, column 4
-- Equation name is '_LC7_C17', type is buried
_LC7_C17 = DFFE( _EQ038, 20Mhz, VCC, VCC, VCC);
_EQ038 = _LC2_C24 & !_LC4_C17 & !_LC7_C17
# !_LC6_C17 & !_LC7_C17;
-- Node name is '|urat:1|s_clk:40|fp1' from file "s_clk.tdf" line 8, column 4
-- Equation name is '_LC5_C17', type is buried
_LC5_C17 = DFFE( _EQ039, 20Mhz, VCC, VCC, VCC);
_EQ039 = !_LC2_C17 & !_LC5_C17 & _LC7_C17
# !_LC2_C17 & _LC5_C17 & !_LC7_C17;
-- Node name is '|urat:1|s_clk:40|fp2' from file "s_clk.tdf" line 8, column 4
-- Equation name is '_LC8_C17', type is buried
_LC8_C17 = DFFE( _EQ040, 20Mhz, VCC, VCC, VCC);
_EQ040 = !_LC2_C17 & !_LC4_C17 & _LC8_C17
# !_LC2_C17 & _LC4_C17 & !_LC8_C17;
-- Node name is '|urat:1|s_clk:40|fp3' from file "s_clk.tdf" line 8, column 4
-- Equation name is '_LC4_C24', type is buried
_LC4_C24 = DFFE( _EQ041, 20Mhz, VCC, VCC, VCC);
_EQ041 = !_LC1_C17 & !_LC2_C17 & _LC4_C24
# _LC1_C17 & !_LC2_C17 & !_LC4_C24;
-- Node name is '|urat:1|s_clk:40|fp4' from file "s_clk.tdf" line 8, column 4
-- Equation name is '_LC5_C24', type is buried
_LC5_C24 = DFFE( _EQ042, 20Mhz, VCC, VCC, VCC);
_EQ042 = !_LC2_C17 & !_LC4_C24 & _LC5_C24
# !_LC1_C17 & !_LC2_C17 & _LC5_C24
# _LC1_C17 & !_LC2_C17 & _LC4_C24 & !_LC5_C24;
-- Node name is '|urat:1|s_clk:40|fp5' from file "s_clk.tdf" line 8, column 4
-- Equation name is '_LC7_C24', type is buried
_LC7_C24 = DFFE( _EQ043, 20Mhz, VCC, VCC, VCC);
_EQ043 = !_LC2_C17 & !_LC6_C24 & _LC7_C24
# !_LC2_C17 & !_LC5_C24 & _LC7_C24
# !_LC2_C17 & _LC5_C24 & _LC6_C24 & !_LC7_C24;
-- Node name is '|urat:1|s_clk:40|fp6' from file "s_clk.tdf" line 8, column 4
-- Equation name is '_LC3_C24', type is buried
_LC3_C24 = DFFE( _EQ044, 20Mhz, VCC, VCC, VCC);
_EQ044 = !_LC2_C17 & _LC3_C24 & !_LC8_C24
# !_LC2_C17 & !_LC3_C24 & _LC8_C24;
-- Node name is '|urat:1|s_clk:40|fp7' from file "s_clk.tdf" line 8, column 4
-- Equation name is '_LC6_C17', type is buried
_LC6_C17 = DFFE( _EQ045, 20Mhz, VCC, VCC, VCC);
_EQ045 = !_LC2_C17 & !_LC3_C24 & _LC6_C17
# !_LC2_C17 & _LC6_C17 & !_LC8_C24
# !_LC2_C17 & _LC3_C24 & !_LC6_C17 & _LC8_C24;
-- Node name is '|urat:1|s_clk:40|:44' from file "s_clk.tdf" line 11, column 13
-- Equation name is '_LC3_C17', type is buried
!_LC3_C17 = _LC3_C17~NOT;
_LC3_C17~NOT = LCELL( _EQ046);
_EQ046 = _LC2_C24 & !_LC5_C17 & !_LC6_C17 & _LC7_C17;
-- Node name is '|urat:1|s_clk:40|:47' from file "s_clk.tdf" line 13, column 10
-- Equation name is '_LC4_C17', type is buried
_LC4_C17 = LCELL( _EQ047);
_EQ047 = _LC5_C17 & _LC7_C17;
-- Node name is '|urat:1|s_clk:40|~53~1' from file "s_clk.tdf" line 13, column 10
-- Equation name is '_LC1_C24', type is buried
-- synthesized logic cell
_LC1_C24 = LCELL( _EQ048);
_EQ048 = !_LC4_C24 & !_LC5_C24 & !_LC8_C17;
-- Node name is '|urat:1|s_clk:40|~53~2' from file "s_clk.tdf" line 13, column 10
-- Equation name is '_LC2_C24', type is buried
-- synthesized logic cell
_LC2_C24 = LCELL( _EQ049);
_EQ049 = _LC1_C24 & !_LC3_C24 & !_LC7_C24;
-- Node name is '|urat:1|s_clk:40|:55' from file "s_clk.tdf" line 13, column 10
-- Equation name is '_LC2_C17', type is buried
!_LC2_C17 = _LC2_C17~NOT;
_LC2_C17~NOT = LCELL( _EQ050);
_EQ050 = !_LC6_C17
# _LC2_C24 & !_LC4_C17;
-- Node name is '|urat:1|s_clk:40|:66' from file "s_clk.tdf" line 16, column 14
-- Equation name is '_LC1_C17', type is buried
_LC1_C17 = LCELL( _EQ051);
_EQ051 = _LC4_C17 & _LC8_C17;
-- Node name is '|urat:1|s_clk:40|:70' from file "s_clk.tdf" line 16, column 14
-- Equation name is '_LC6_C24', type is buried
_LC6_C24 = LCELL( _EQ052);
_EQ052 = _LC1_C17 & _LC4_C24;
-- Node name is '|urat:1|s_clk:40|:78' from file "s_clk.tdf" line 16, column 14
-- Equation name is '_LC8_C24', type is buried
_LC8_C24 = LCELL( _EQ053);
_EQ053 = _LC1_C17 & _LC4_C24 & _LC5_C24 & _LC7_C24;
-- Node name is '|urat:1|:29'
-- Equation name is '_LC5_B2', type is buried
_LC5_B2 = LCELL( _EQ054);
_EQ054 = !Js_Rxd & _LC3_B3 & !_LC4_B3 & !_LC8_B2;
-- Node name is ':23'
-- Equation name is '_LC6_B23', type is buried
_LC6_B23 = LCELL( _EQ055);
_EQ055 = Fs_load & _LC5_B23
# Fs_load & !_LC4_B23;
Project Information d:\maxplus2\file\uart\top.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,882K
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