📄 top.rpt
字号:
22 - - B -- OUTPUT 0 1 0 0 js_po2
21 - - B -- OUTPUT 0 1 0 0 js_po3
19 - - A -- OUTPUT 0 1 0 0 js_po4
18 - - A -- OUTPUT 0 1 0 0 js_po5
17 - - A -- OUTPUT 0 1 0 0 js_po6
16 - - A -- OUTPUT 0 1 0 0 js_po7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\maxplus2\file\uart\top.rpt
top
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - B 23 DFFE 0 2 0 2 |g1p:40|:1
- 5 - B 23 DFFE 0 3 0 1 |g1p:40|:2
- 1 - B 22 DFFE 0 1 0 4 |m1024:43|fp0
- 2 - B 18 DFFE 0 2 0 3 |m1024:43|fp1
- 3 - B 18 DFFE 0 3 0 2 |m1024:43|fp2
- 4 - B 18 DFFE 0 4 0 1 |m1024:43|fp3
- 6 - B 18 DFFE 0 2 0 3 |m1024:43|fp4
- 7 - B 18 DFFE 0 3 0 2 |m1024:43|fp5
- 8 - B 18 DFFE 0 4 0 1 |m1024:43|fp6
- 7 - B 23 DFFE 0 2 0 2 |m1024:43|fp7
- 8 - B 23 DFFE 0 3 0 1 |m1024:43|fp8
- 1 - B 23 DFFE 0 4 1 2 |m1024:43|fp9
- 5 - B 18 AND2 0 4 0 4 |m1024:43|:53
- 1 - B 18 AND2 0 4 0 3 |m1024:43|:65
- 5 - B 14 DFFE 0 3 0 4 |urat:1|fs_cnt:113|cnt0
- 8 - B 14 DFFE 0 4 0 4 |urat:1|fs_cnt:113|cnt1
- 6 - B 14 DFFE 0 5 0 3 |urat:1|fs_cnt:113|cnt2
- 4 - B 14 DFFE 0 5 0 2 |urat:1|fs_cnt:113|cnt3
- 1 - B 19 DFFE 0 2 0 2 |urat:1|fs_cnt:113|cnt4
- 2 - B 14 OR2 ! 0 4 0 4 |urat:1|fs_cnt:113|:50
- 3 - B 14 AND2 0 2 0 1 |urat:1|fs_cnt:113|:57
- 1 - B 14 OR2 s 0 3 0 1 |urat:1|fs_cnt:113|~95~1
- 7 - B 14 OR2 0 3 1 1 |urat:1|fs_cnt:113|:95
- 4 - B 10 DFFE ! 0 3 1 0 |urat:1|fs_sft:115|sft_reg0
- 8 - B 10 DFFE 0 3 0 1 |urat:1|fs_sft:115|sft_reg1
- 7 - B 10 DFFE 1 3 0 1 |urat:1|fs_sft:115|sft_reg2
- 6 - B 10 DFFE 1 3 0 1 |urat:1|fs_sft:115|sft_reg3
- 5 - B 10 DFFE 1 3 0 1 |urat:1|fs_sft:115|sft_reg4
- 3 - B 10 DFFE 1 3 0 1 |urat:1|fs_sft:115|sft_reg5
- 2 - B 10 DFFE 1 3 0 1 |urat:1|fs_sft:115|sft_reg6
- 1 - B 10 DFFE 1 3 0 1 |urat:1|fs_sft:115|sft_reg7
- 2 - B 19 DFFE 1 3 0 1 |urat:1|fs_sft:115|sft_reg8
- 8 - B 19 DFFE 1 2 0 1 |urat:1|fs_sft:115|sft_reg9
- 6 - B 02 DFFE 0 2 0 2 |urat:1|g1p:77|:1
- 7 - B 02 DFFE 0 3 0 1 |urat:1|g1p:77|:2
- 3 - B 02 OR2 ! 0 2 0 8 |urat:1|g1p:77|1p (|urat:1|g1p:77|:3)
- 3 - B 23 DFFE 0 2 0 2 |urat:1|g1p:116|:1
- 2 - B 23 DFFE 0 3 0 1 |urat:1|g1p:116|:2
- 5 - B 12 DFFE 0 2 1 0 |urat:1|js_sft:95|js_buf0
- 4 - B 12 DFFE 0 2 1 0 |urat:1|js_sft:95|js_buf1
- 2 - B 12 DFFE 0 2 1 0 |urat:1|js_sft:95|js_buf2
- 1 - B 12 DFFE 0 2 1 0 |urat:1|js_sft:95|js_buf3
- 7 - B 12 DFFE 0 2 1 0 |urat:1|js_sft:95|js_buf4
- 8 - B 08 DFFE 0 2 1 0 |urat:1|js_sft:95|js_buf5
- 3 - B 12 DFFE 0 2 1 0 |urat:1|js_sft:95|js_buf6
- 1 - B 08 DFFE 0 2 1 0 |urat:1|js_sft:95|js_buf7
- 8 - B 12 DFFE 0 2 0 1 |urat:1|js_sft:95|sft_reg1
- 6 - B 12 DFFE 0 2 0 2 |urat:1|js_sft:95|sft_reg2
- 2 - B 06 DFFE 0 2 0 2 |urat:1|js_sft:95|sft_reg3
- 3 - B 06 DFFE 0 2 0 2 |urat:1|js_sft:95|sft_reg4
- 4 - B 06 DFFE 0 2 0 2 |urat:1|js_sft:95|sft_reg5
- 5 - B 06 DFFE 0 2 0 2 |urat:1|js_sft:95|sft_reg6
- 6 - B 06 DFFE 0 2 0 2 |urat:1|js_sft:95|sft_reg7
- 7 - B 06 DFFE 0 2 0 2 |urat:1|js_sft:95|sft_reg8
- 8 - B 06 DFFE 1 1 0 1 |urat:1|js_sft:95|sft_reg9
- 6 - B 03 DFFE 0 3 0 3 |urat:1|js_tb:93|jsck0
- 5 - B 03 DFFE 0 4 0 2 |urat:1|js_tb:93|jsck1
- 7 - B 03 DFFE 0 5 0 1 |urat:1|js_tb:93|jsck2
- 1 - B 06 DFFE 0 4 0 11 |urat:1|js_tb:93|jsck3
- 8 - B 02 DFFE 0 5 0 3 |urat:1|js_tb:93|jsck4
- 2 - B 02 DFFE 0 5 0 4 |urat:1|js_tb:93|jsck5
- 4 - B 03 DFFE 0 5 0 4 |urat:1|js_tb:93|jsck6
- 8 - B 03 DFFE 0 5 0 3 |urat:1|js_tb:93|jsck7
- 1 - B 03 OR2 ! 0 3 0 6 |urat:1|js_tb:93|:54
- 2 - B 03 AND2 0 3 0 3 |urat:1|js_tb:93|:65
- 1 - B 02 AND2 0 3 0 3 |urat:1|js_tb:93|:73
- 3 - B 03 AND2 0 2 0 3 |urat:1|js_tb:93|:110
- 4 - B 02 AND2 ! 0 3 0 8 |urat:1|js_tb:93|:122
- 5 - B 19 DFFE 0 1 0 3 |urat:1|m16:25|fp0
- 6 - B 19 DFFE 0 2 0 2 |urat:1|m16:25|fp1
- 7 - B 19 DFFE 0 3 0 1 |urat:1|m16:25|fp2
- 4 - B 19 DFFE 0 4 0 29 |urat:1|m16:25|fp3
- 7 - C 17 DFFE 1 3 0 3 |urat:1|s_clk:40|fp0
- 5 - C 17 DFFE 1 2 0 2 |urat:1|s_clk:40|fp1
- 8 - C 17 DFFE 1 2 0 2 |urat:1|s_clk:40|fp2
- 4 - C 24 DFFE 1 2 0 4 |urat:1|s_clk:40|fp3
- 5 - C 24 DFFE 1 3 0 3 |urat:1|s_clk:40|fp4
- 7 - C 24 DFFE 1 3 0 2 |urat:1|s_clk:40|fp5
- 3 - C 24 DFFE 1 2 0 2 |urat:1|s_clk:40|fp6
- 6 - C 17 DFFE 1 3 0 3 |urat:1|s_clk:40|fp7
- 3 - C 17 AND2 ! 0 4 0 14 |urat:1|s_clk:40|:44
- 4 - C 17 AND2 0 2 0 4 |urat:1|s_clk:40|:47
- 1 - C 24 AND2 s 0 3 0 1 |urat:1|s_clk:40|~53~1
- 2 - C 24 AND2 s 0 3 0 3 |urat:1|s_clk:40|~53~2
- 2 - C 17 OR2 ! 0 3 0 7 |urat:1|s_clk:40|:55
- 1 - C 17 AND2 0 2 0 4 |urat:1|s_clk:40|:66
- 6 - C 24 AND2 0 2 0 1 |urat:1|s_clk:40|:70
- 8 - C 24 AND2 0 4 0 2 |urat:1|s_clk:40|:78
- 5 - B 02 AND2 1 3 0 2 |urat:1|:29
- 3 - B 19 OR2 ! 0 3 0 15 |urat:1|fs_ld (|urat:1|:117)
- 6 - B 23 OR2 1 2 0 2 :23
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\maxplus2\file\uart\top.rpt
top
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 4/ 48( 8%) 1/ 48( 2%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
B: 14/ 96( 14%) 16/ 48( 33%) 7/ 48( 14%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 3/ 96( 3%) 0/ 48( 0%) 6/ 48( 12%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\maxplus2\file\uart\top.rpt
top
** CLOCK SIGNALS **
Type Fan-out Name
DFF 30 |urat:1|m16:25|fp3
LCELL 14 |urat:1|s_clk:40|:44
DFF 12 |urat:1|js_tb:93|jsck3
LCELL 8 |urat:1|js_tb:93|:122
INPUT 8 20Mhz
Device-Specific Information: d:\maxplus2\file\uart\top.rpt
top
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 15 |urat:1|fs_ld
LCELL 8 |urat:1|g1p:77|1p
DFF 4 |m1024:43|fp9
LCELL 2 |urat:1|:29
LCELL 2 :23
Device-Specific Information: d:\maxplus2\file\uart\top.rpt
top
** EQUATIONS **
Fs_load : INPUT;
Fs_pi0 : INPUT;
Fs_pi1 : INPUT;
Fs_pi2 : INPUT;
Fs_pi3 : INPUT;
Fs_pi4 : INPUT;
Fs_pi5 : INPUT;
Fs_pi6 : INPUT;
Fs_pi7 : INPUT;
Js_Rxd : INPUT;
20Mhz : INPUT;
-- Node name is 'auto'
-- Equation name is 'auto', type is output
auto = _LC1_B23;
-- Node name is 'fs_dao'
-- Equation name is 'fs_dao', type is output
fs_dao = !_LC7_B14;
-- Node name is 'Fs_Txd'
-- Equation name is 'Fs_Txd', type is output
Fs_Txd = _LC4_B10;
-- Node name is 'js_po0'
-- Equation name is 'js_po0', type is output
js_po0 = _LC5_B12;
-- Node name is 'js_po1'
-- Equation name is 'js_po1', type is output
js_po1 = _LC4_B12;
-- Node name is 'js_po2'
-- Equation name is 'js_po2', type is output
js_po2 = _LC2_B12;
-- Node name is 'js_po3'
-- Equation name is 'js_po3', type is output
js_po3 = _LC1_B12;
-- Node name is 'js_po4'
-- Equation name is 'js_po4', type is output
js_po4 = _LC7_B12;
-- Node name is 'js_po5'
-- Equation name is 'js_po5', type is output
js_po5 = _LC8_B8;
-- Node name is 'js_po6'
-- Equation name is 'js_po6', type is output
js_po6 = _LC3_B12;
-- Node name is 'js_po7'
-- Equation name is 'js_po7', type is output
js_po7 = _LC1_B8;
-- Node name is '|g1p:40|:1'
-- Equation name is '_LC4_B23', type is buried
_LC4_B23 = DFFE( VCC, _LC4_B19, _LC1_B23, VCC, VCC);
-- Node name is '|g1p:40|:2'
-- Equation name is '_LC5_B23', type is buried
_LC5_B23 = DFFE( _LC4_B23, !_LC4_B19, _LC1_B23, VCC, VCC);
-- Node name is '|m1024:43|fp0' from file "m1024.tdf" line 8, column 4
-- Equation name is '_LC1_B22', type is buried
_LC1_B22 = DFFE(!_LC1_B22, _LC4_B19, VCC, VCC, VCC);
-- Node name is '|m1024:43|fp1' from file "m1024.tdf" line 8, column 4
-- Equation name is '_LC2_B18', type is buried
_LC2_B18 = DFFE( _EQ001, _LC4_B19, VCC, VCC, VCC);
_EQ001 = _LC1_B22 & !_LC2_B18
# !_LC1_B22 & _LC2_B18;
-- Node name is '|m1024:43|fp2' from file "m1024.tdf" line 8, column 4
-- Equation name is '_LC3_B18', type is buried
_LC3_B18 = DFFE( _EQ002, _LC4_B19, VCC, VCC, VCC);
_EQ002 = !_LC1_B22 & _LC3_B18
# !_LC2_B18 & _LC3_B18
# _LC1_B22 & _LC2_B18 & !_LC3_B18;
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