📄 fs_test.rpt
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12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\maxplus2\file\uart\fs_test.rpt
fs_test
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 19 fs_clock
Device-Specific Information: d:\maxplus2\file\uart\fs_test.rpt
fs_test
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 17 :4
INPUT 2 Fs_load
Device-Specific Information: d:\maxplus2\file\uart\fs_test.rpt
fs_test
** EQUATIONS **
fs_clock : INPUT;
Fs_load : INPUT;
Fs_pi0 : INPUT;
Fs_pi1 : INPUT;
Fs_pi2 : INPUT;
Fs_pi3 : INPUT;
Fs_pi4 : INPUT;
Fs_pi5 : INPUT;
Fs_pi6 : INPUT;
Fs_pi7 : INPUT;
-- Node name is 'fs_clk'
-- Equation name is 'fs_clk', type is output
fs_clk = _LC7_B13;
-- Node name is 'fs_clk~1'
-- Equation name is 'fs_clk~1', location is LC7_B13, type is buried.
-- synthesized logic cell
_LC7_B13 = LCELL( fs_clock);
-- Node name is 'fs_dao'
-- Equation name is 'fs_dao', type is output
fs_dao = !_LC1_C17;
-- Node name is 'fs_ld'
-- Equation name is 'fs_ld', type is output
fs_ld = _LC5_C17;
-- Node name is 'Fs_po0'
-- Equation name is 'Fs_po0', type is output
Fs_po0 = _LC7_C5;
-- Node name is 'Fs_po1'
-- Equation name is 'Fs_po1', type is output
Fs_po1 = _LC6_C5;
-- Node name is 'Fs_po2'
-- Equation name is 'Fs_po2', type is output
Fs_po2 = _LC4_C5;
-- Node name is 'Fs_po3'
-- Equation name is 'Fs_po3', type is output
Fs_po3 = _LC3_C5;
-- Node name is 'Fs_po4'
-- Equation name is 'Fs_po4', type is output
Fs_po4 = _LC5_C5;
-- Node name is 'Fs_po5'
-- Equation name is 'Fs_po5', type is output
Fs_po5 = _LC2_C5;
-- Node name is 'Fs_po6'
-- Equation name is 'Fs_po6', type is output
Fs_po6 = _LC1_C5;
-- Node name is 'Fs_po7'
-- Equation name is 'Fs_po7', type is output
Fs_po7 = _LC2_C16;
-- Node name is 'Fs_po8'
-- Equation name is 'Fs_po8', type is output
Fs_po8 = _LC4_C16;
-- Node name is 'Fs_po9'
-- Equation name is 'Fs_po9', type is output
Fs_po9 = _LC6_C16;
-- Node name is 'Fs_Txd'
-- Equation name is 'Fs_Txd', type is output
Fs_Txd = _LC8_C5;
-- Node name is 'fs_1p'
-- Equation name is 'fs_1p', type is output
fs_1p = _LC2_C17;
-- Node name is '|fs_cnt:2|cnt0' from file "fs_cnt.tdf" line 8, column 5
-- Equation name is '_LC1_C16', type is buried
_LC1_C16 = DFFE( _EQ001, GLOBAL( fs_clock), !_LC5_C17, VCC, VCC);
_EQ001 = !_LC1_C16 & _LC3_C17
# _LC1_C16 & !_LC3_C17;
-- Node name is '|fs_cnt:2|cnt1' from file "fs_cnt.tdf" line 8, column 5
-- Equation name is '_LC3_C16', type is buried
_LC3_C16 = DFFE( _EQ002, GLOBAL( fs_clock), !_LC5_C17, VCC, VCC);
_EQ002 = _LC3_C16 & !_LC3_C17
# !_LC1_C16 & _LC3_C16
# _LC1_C16 & !_LC3_C16 & _LC3_C17;
-- Node name is '|fs_cnt:2|cnt2' from file "fs_cnt.tdf" line 8, column 5
-- Equation name is '_LC5_C16', type is buried
_LC5_C16 = DFFE( _EQ003, GLOBAL( fs_clock), !_LC5_C17, VCC, VCC);
_EQ003 = !_LC3_C16 & _LC5_C16
# !_LC1_C16 & _LC5_C16
# _LC1_C16 & _LC3_C16 & _LC3_C17 & !_LC5_C16
# !_LC3_C17 & _LC5_C16;
-- Node name is '|fs_cnt:2|cnt3' from file "fs_cnt.tdf" line 8, column 5
-- Equation name is '_LC7_C16', type is buried
_LC7_C16 = DFFE( _EQ004, GLOBAL( fs_clock), !_LC5_C17, VCC, VCC);
_EQ004 = !_LC3_C17 & _LC7_C16
# !_LC5_C16 & _LC7_C16
# _LC7_C16 & !_LC8_C16
# _LC3_C17 & _LC5_C16 & !_LC7_C16 & _LC8_C16;
-- Node name is '|fs_cnt:2|cnt4' from file "fs_cnt.tdf" line 8, column 5
-- Equation name is '_LC6_C17', type is buried
_LC6_C17 = DFFE( _LC6_C17, GLOBAL( fs_clock), !_LC5_C17, VCC, VCC);
-- Node name is '|fs_cnt:2|:50' from file "fs_cnt.tdf" line 14, column 11
-- Equation name is '_LC3_C17', type is buried
!_LC3_C17 = _LC3_C17~NOT;
_LC3_C17~NOT = LCELL( _EQ005);
_EQ005 = _LC5_C16 & _LC7_C16
# _LC3_C16 & _LC7_C16
# _LC6_C17;
-- Node name is '|fs_cnt:2|:57' from file "fs_cnt.tdf" line 15, column 19
-- Equation name is '_LC8_C16', type is buried
_LC8_C16 = LCELL( _EQ006);
_EQ006 = _LC1_C16 & _LC3_C16;
-- Node name is '|fs_cnt:2|~95~1' from file "fs_cnt.tdf" line 20, column 15
-- Equation name is '_LC4_C17', type is buried
-- synthesized logic cell
_LC4_C17 = LCELL( _EQ007);
_EQ007 = !_LC7_C16
# _LC1_C16
# _LC6_C17;
-- Node name is '|fs_cnt:2|:95' from file "fs_cnt.tdf" line 20, column 15
-- Equation name is '_LC1_C17', type is buried
_LC1_C17 = LCELL( _EQ008);
_EQ008 = _LC5_C16
# !_LC3_C16
# _LC4_C17;
-- Node name is '|fs_sft:1|sft_reg0~1' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC8_C5', type is buried
-- synthesized logic cell
!_LC8_C5 = _LC8_C5~NOT;
_LC8_C5~NOT = DFFE(!_LC6_C5, GLOBAL( fs_clock), !_LC5_C17, VCC, VCC);
-- Node name is '|fs_sft:1|sft_reg0' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC7_C5', type is buried
!_LC7_C5 = _LC7_C5~NOT;
_LC7_C5~NOT = DFFE(!_LC6_C5, GLOBAL( fs_clock), !_LC5_C17, VCC, VCC);
-- Node name is '|fs_sft:1|sft_reg1' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC6_C5', type is buried
_LC6_C5 = DFFE( _LC4_C5, GLOBAL( fs_clock), !_LC5_C17, VCC, VCC);
-- Node name is '|fs_sft:1|sft_reg2' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC4_C5', type is buried
_LC4_C5 = DFFE( _LC3_C5, GLOBAL( fs_clock), !( _LC5_C17 & !Fs_pi0), !( _LC5_C17 & Fs_pi0), VCC);
-- Node name is '|fs_sft:1|sft_reg3' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC3_C5', type is buried
_LC3_C5 = DFFE( _LC5_C5, GLOBAL( fs_clock), !( _LC5_C17 & !Fs_pi1), !( _LC5_C17 & Fs_pi1), VCC);
-- Node name is '|fs_sft:1|sft_reg4' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC5_C5', type is buried
_LC5_C5 = DFFE( _LC2_C5, GLOBAL( fs_clock), !( _LC5_C17 & !Fs_pi2), !( _LC5_C17 & Fs_pi2), VCC);
-- Node name is '|fs_sft:1|sft_reg5' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC2_C5', type is buried
_LC2_C5 = DFFE( _LC1_C5, GLOBAL( fs_clock), !( _LC5_C17 & !Fs_pi3), !( _LC5_C17 & Fs_pi3), VCC);
-- Node name is '|fs_sft:1|sft_reg6' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC1_C5', type is buried
_LC1_C5 = DFFE( _LC2_C16, GLOBAL( fs_clock), !( _LC5_C17 & !Fs_pi4), !( _LC5_C17 & Fs_pi4), VCC);
-- Node name is '|fs_sft:1|sft_reg7' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC2_C16', type is buried
_LC2_C16 = DFFE( _LC4_C16, GLOBAL( fs_clock), !( _LC5_C17 & !Fs_pi5), !( _LC5_C17 & Fs_pi5), VCC);
-- Node name is '|fs_sft:1|sft_reg8' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC4_C16', type is buried
_LC4_C16 = DFFE( _LC6_C16, GLOBAL( fs_clock), !( _LC5_C17 & !Fs_pi6), !( _LC5_C17 & Fs_pi6), VCC);
-- Node name is '|fs_sft:1|sft_reg9' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC6_C16', type is buried
_LC6_C16 = DFFE( VCC, GLOBAL( fs_clock), !( _LC5_C17 & !Fs_pi7), !( _LC5_C17 & Fs_pi7), VCC);
-- Node name is '|g1p:3|:1'
-- Equation name is '_LC7_C17', type is buried
_LC7_C17 = DFFE( VCC, GLOBAL( fs_clock), GLOBAL( Fs_load), VCC, VCC);
-- Node name is '|g1p:3|:3' = '|g1p:3|1p'
-- Equation name is '_LC2_C17', type is buried
!_LC2_C17 = _LC2_C17~NOT;
_LC2_C17~NOT = LCELL( _EQ009);
_EQ009 = !_LC7_C17
# _LC8_C17;
-- Node name is '|g1p:3|:2'
-- Equation name is '_LC8_C17', type is buried
_LC8_C17 = DFFE( _LC7_C17, GLOBAL(!fs_clock), GLOBAL( Fs_load), VCC, VCC);
-- Node name is ':4'
-- Equation name is '_LC5_C17', type is buried
!_LC5_C17 = _LC5_C17~NOT;
_LC5_C17~NOT = LCELL( _EQ010);
_EQ010 = _LC1_C17
# !_LC2_C17;
Project Information d:\maxplus2\file\uart\fs_test.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,865K
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