📄 fs_sft.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\maxplus2\file\uart\fs_sft.rpt
fs_sft
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 0/ 48( 0%) 5/ 48( 10%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\maxplus2\file\uart\fs_sft.rpt
fs_sft
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 11 clk
Device-Specific Information: d:\maxplus2\file\uart\fs_sft.rpt
fs_sft
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 11 load
Device-Specific Information: d:\maxplus2\file\uart\fs_sft.rpt
fs_sft
** EQUATIONS **
clk : INPUT;
load : INPUT;
pi0 : INPUT;
pi1 : INPUT;
pi2 : INPUT;
pi3 : INPUT;
pi4 : INPUT;
pi5 : INPUT;
pi6 : INPUT;
pi7 : INPUT;
-- Node name is 'po0' from file "fs_sft.tdf" line 20, column 4
-- Equation name is 'po0', type is output
po0 = sft_reg0;
-- Node name is 'po1' from file "fs_sft.tdf" line 20, column 4
-- Equation name is 'po1', type is output
po1 = sft_reg1;
-- Node name is 'po2' from file "fs_sft.tdf" line 20, column 4
-- Equation name is 'po2', type is output
po2 = sft_reg2;
-- Node name is 'po3' from file "fs_sft.tdf" line 20, column 4
-- Equation name is 'po3', type is output
po3 = sft_reg3;
-- Node name is 'po4' from file "fs_sft.tdf" line 20, column 4
-- Equation name is 'po4', type is output
po4 = sft_reg4;
-- Node name is 'po5' from file "fs_sft.tdf" line 20, column 4
-- Equation name is 'po5', type is output
po5 = sft_reg5;
-- Node name is 'po6' from file "fs_sft.tdf" line 20, column 4
-- Equation name is 'po6', type is output
po6 = sft_reg6;
-- Node name is 'po7' from file "fs_sft.tdf" line 20, column 4
-- Equation name is 'po7', type is output
po7 = sft_reg7;
-- Node name is 'po8' from file "fs_sft.tdf" line 20, column 4
-- Equation name is 'po8', type is output
po8 = sft_reg8;
-- Node name is 'po9' from file "fs_sft.tdf" line 20, column 4
-- Equation name is 'po9', type is output
po9 = sft_reg9;
-- Node name is 'sft_reg0~1' from file "fs_sft.tdf" line 10, column 9
-- Equation name is 'sft_reg0~1', location is LC3_B22, type is buried.
-- synthesized logic cell
!_LC3_B22 = _LC3_B22~NOT;
_LC3_B22~NOT = DFFE(!sft_reg1, GLOBAL( clk), GLOBAL(!load), VCC, VCC);
-- Node name is 'sft_reg0' from file "fs_sft.tdf" line 10, column 9
-- Equation name is 'sft_reg0', location is LC1_B22, type is buried.
!sft_reg0 = sft_reg0~NOT;
sft_reg0~NOT = DFFE(!sft_reg1, GLOBAL( clk), GLOBAL(!load), VCC, VCC);
-- Node name is 'sft_reg1' from file "fs_sft.tdf" line 10, column 9
-- Equation name is 'sft_reg1', location is LC8_B22, type is buried.
sft_reg1 = DFFE( sft_reg2, GLOBAL( clk), GLOBAL(!load), VCC, VCC);
-- Node name is 'sft_reg2' from file "fs_sft.tdf" line 10, column 9
-- Equation name is 'sft_reg2', location is LC6_B22, type is buried.
sft_reg2 = DFFE( sft_reg3, GLOBAL( clk), !(GLOBAL( load) & !pi0), !(GLOBAL( load) & pi0), VCC);
-- Node name is 'sft_reg3' from file "fs_sft.tdf" line 10, column 9
-- Equation name is 'sft_reg3', location is LC2_A13, type is buried.
sft_reg3 = DFFE( sft_reg4, GLOBAL( clk), !(GLOBAL( load) & !pi1), !(GLOBAL( load) & pi1), VCC);
-- Node name is 'sft_reg4' from file "fs_sft.tdf" line 10, column 9
-- Equation name is 'sft_reg4', location is LC8_A13, type is buried.
sft_reg4 = DFFE( sft_reg5, GLOBAL( clk), !(GLOBAL( load) & !pi2), !(GLOBAL( load) & pi2), VCC);
-- Node name is 'sft_reg5' from file "fs_sft.tdf" line 10, column 9
-- Equation name is 'sft_reg5', location is LC6_A13, type is buried.
sft_reg5 = DFFE( sft_reg6, GLOBAL( clk), !(GLOBAL( load) & !pi3), !(GLOBAL( load) & pi3), VCC);
-- Node name is 'sft_reg6' from file "fs_sft.tdf" line 10, column 9
-- Equation name is 'sft_reg6', location is LC5_A13, type is buried.
sft_reg6 = DFFE( sft_reg7, GLOBAL( clk), !(GLOBAL( load) & !pi4), !(GLOBAL( load) & pi4), VCC);
-- Node name is 'sft_reg7' from file "fs_sft.tdf" line 10, column 9
-- Equation name is 'sft_reg7', location is LC1_A13, type is buried.
sft_reg7 = DFFE( sft_reg8, GLOBAL( clk), !(GLOBAL( load) & !pi5), !(GLOBAL( load) & pi5), VCC);
-- Node name is 'sft_reg8' from file "fs_sft.tdf" line 10, column 9
-- Equation name is 'sft_reg8', location is LC3_A13, type is buried.
sft_reg8 = DFFE( sft_reg9, GLOBAL( clk), !(GLOBAL( load) & !pi6), !(GLOBAL( load) & pi6), VCC);
-- Node name is 'sft_reg9' from file "fs_sft.tdf" line 10, column 9
-- Equation name is 'sft_reg9', location is LC4_A13, type is buried.
sft_reg9 = DFFE( VCC, GLOBAL( clk), !(GLOBAL( load) & !pi7), !(GLOBAL( load) & pi7), VCC);
-- Node name is 'so' from file "fs_sft.tdf" line 21, column 2
-- Equation name is 'so', type is output
so = _LC3_B22;
Project Information d:\maxplus2\file\uart\fs_sft.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,919K
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