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📄 sinmdl.mdl

📁 正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过
💻 MDL
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    }
    PropName		    "ConfigurationSets"
  }
  Simulink.ConfigSet {
    $PropName		    "ActiveConfigurationSet"
    $ObjectID		    1
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  BlockDefaults {
    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
  }
  BlockParameterDefaults {
    Block {
      BlockType		      Mux
      Inputs		      "4"
      DisplayOption	      "none"
      BusObject		      "BusObject"
      NonVirtualBus	      off
    }
    Block {
      BlockType		      RandomNumber
      Mean		      "0"
      Variance		      "1"
      Seed		      "0"
      SampleTime	      "-1"
      VectorParams1D	      on
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    Block {
      BlockType		      Scope
      Floating		      off
      ModelBased	      off
      TickLabels	      "OneTimeTick"
      ZoomMode		      "on"
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      TimeRange		      "auto"
      YMin		      "-5"
      YMax		      "5"
      SaveToWorkspace	      off
      SaveName		      "ScopeData"
      LimitDataPoints	      on
      MaxDataPoints	      "5000"
      Decimation	      "1"
      SampleInput	      off
      SampleTime	      "0"
    }
    Block {
      BlockType		      "S-Function"
      FunctionName	      "system"
      SFunctionModules	      "''"
      PortCounts	      "[]"
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    Block {
      BlockType		      Sin
      SineType		      "Time based"
      TimeSource	      "Use simulation time"
      Amplitude		      "1"
      Bias		      "0"
      Frequency		      "1"
      Phase		      "0"
      Samples		      "10"
      Offset		      "0"
      SampleTime	      "-1"
      VectorParams1D	      on
    }
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  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "sinmdl"
    Location		    [-74, 143, 681, 728]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "A4"
    PaperUnits		    "centimeters"
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      Reference
      Name		      "BusBuild"
      Ports		      [2, 1]
      Position		      [340, 409, 380, 531]
      ForegroundColor	      "blue"
      SourceBlock	      "bus_alteradspbuilder/BusBuild"
      SourceType	      "BuildBus AlteraBlockSet"
      BusType		      "Signed Integer"
      bwl		      "2"
      bwr		      "0"
    }
    Block {
      BlockType		      Reference
      Name		      "Delay"
      Ports		      [1, 1]
      Position		      [315, 265, 360, 315]
      ForegroundColor	      "blue"
      SourceBlock	      "store_alteradspbuilder/Delay"
      SourceType	      "Delay AlteraBlockSet"
      depth		      "1"
      clken		      off
      MaskValue		      "01"
    }
    Block {
      BlockType		      Reference
      Name		      "GND"
      Ports		      [0, 1]
      Position		      [240, 491, 255, 509]
      ForegroundColor	      "blue"
      ShowName		      off
      SourceBlock	      "bus_alteradspbuilder/GND"
      SourceType	      "SGND AlteraBlockSet"
      ncstsamp		      "1"
    }
    Block {
      BlockType		      Mux
      Name		      "Mux"
      Ports		      [2, 1]
      Position		      [505, 261, 510, 299]
      ShowName		      off
      Inputs		      "2"
      DisplayOption	      "bar"
    }
    Block {
      BlockType		      Reference
      Name		      "Product"
      Ports		      [2, 1]
      Position		      [445, 418, 510, 467]
      ForegroundColor	      "blue"
      SourceBlock	      "arithm_alteradspbuilder/Product"
      SourceType	      "Product Altera BlockSet"
      pipeline		      "0"
      lpm		      off
      eab		      off
      clken		      off
      MaskValue		      "1"
    }
    Block {
      BlockType		      RandomNumber
      Name		      "Random\nNumber"
      Position		      [130, 425, 160, 455]
      SampleTime	      "25e-9"
    }
    Block {
      BlockType		      Scope
      Name		      "Scope"
      Ports		      [3]
      Position		      [690, 314, 720, 346]
      Location		      [1, 52, 1025, 737]
      Open		      off
      NumInputPorts	      "3"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
	axes2			"%<SignalLabel>"
	axes3			"%<SignalLabel>"
      }
      YMin		      "-5~-5~-5"
      YMax		      "5~5~5"
      DataFormat	      "StructureWithTime"
    }
    Block {
      BlockType		      Reference
      Name		      "SignalCompiler"
      Ports		      []
      Position		      [319, 73, 388, 120]
      ForegroundColor	      "blue"
      SourceBlock	      "ALTELINK/AltLab/SignalCompiler"
      SourceType	      "SignalCompiler"
      family		      "Stratix"
      opt		      "Speed"
      synthtool		      "Others"
      vstim		      on
      SynthAct		      "None"
      workdir		      "f:\\dspbuilder\\mydesign"
      Procetype		      "prod"
      UseReset		      on
      ResetPin		      "Active High"
      ClockPin		      "Output to Pin"
      ClockPeriod	      "20"
      UseSignalTap	      off
      CreatePtfFile	      off
      SignalTapDepth	      "128"
      VerilogSupport	      off
    }
    Block {
      BlockType		      Sin
      Name		      "Sine Wave"
      Ports		      [0, 1]
      Position		      [130, 275, 160, 305]
      SineType		      "Sample based"
      Amplitude		      "2^15-1"
      Samples		      "80"
      SampleTime	      "25e-9"
    }
    Block {
      BlockType		      Reference
      Name		      "noise"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [220, 432, 285, 448]
      ForegroundColor	      "blue"
      SourceBlock	      "bus_alteradspbuilder/Input"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Single Bit"
      nodetype		      "Input Port"
      bwl		      "1"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "noise"
      ppat		      "f:\\dspbuilder\\mydesign\\DSPBuilder_sinmdl"
      nSgCpl		      "1"
    }
    Block {
      BlockType		      Reference
      Name		      "sindelay"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [400, 282, 465, 298]
      ForegroundColor	      "blue"
      SourceBlock	      "bus_alteradspbuilder/Output"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Output Port"
      bwl		      "16"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "Output"
      nSgCpl		      "0"
    }
    Block {
      BlockType		      Reference
      Name		      "sinin"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [215, 282, 280, 298]
      ForegroundColor	      "blue"
      SourceBlock	      "bus_alteradspbuilder/Input"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Input Port"
      bwl		      "16"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "sinin"
      ppat		      "f:\\dspbuilder\\mydesign\\DSPBuilder_sinmdl"
      nSgCpl		      "1"
    }
    Block {
      BlockType		      Reference
      Name		      "streammod"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [545, 437, 610, 453]
      ForegroundColor	      "blue"
      SourceBlock	      "bus_alteradspbuilder/Output"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Output Port"
      bwl		      "19"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "Output"
      nSgCpl		      "0"
    }
    Line {
      SrcBlock		      "Sine Wave"
      SrcPort		      1
      DstBlock		      "sinin"
      DstPort		      1
    }
    Line {
      SrcBlock		      "sinin"
      SrcPort		      1
      Points		      [0, 0]
      Branch {
	DstBlock		"Delay"
	DstPort			1
      }
      Branch {
	Points			[0, -90; 185, 0; 0, 70]
	DstBlock		"Mux"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Delay"
      SrcPort		      1
      Points		      [10, 0]
      Branch {
	DstBlock		"sindelay"
	DstPort			1
      }
      Branch {
	Points			[0, 140]
	DstBlock		"Product"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "sindelay"
      SrcPort		      1
      DstBlock		      "Mux"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Random\nNumber"
      SrcPort		      1
      DstBlock		      "noise"
      DstPort		      1
    }
    Line {
      SrcBlock		      "noise"
      SrcPort		      1
      DstBlock		      "BusBuild"
      DstPort		      1
    }
    Line {
      SrcBlock		      "GND"
      SrcPort		      1
      DstBlock		      "BusBuild"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Product"
      SrcPort		      1
      DstBlock		      "streammod"
      DstPort		      1
    }
    Line {
      SrcBlock		      "BusBuild"
      SrcPort		      1
      Points		      [25, 0]
      Branch {
	Points			[0, 80; 240, 0; 0, -210]
	DstBlock		"Scope"
	DstPort			3
      }
      Branch {
	Points			[0, -15]
	DstBlock		"Product"
	DstPort			2
      }
    }
    Line {
      SrcBlock		      "Mux"
      SrcPort		      1
      Points		      [135, 0; 0, 40]
      DstBlock		      "Scope"
      DstPort		      1
    }
    Line {
      SrcBlock		      "streammod"
      SrcPort		      1
      Points		      [0, -115]
      DstBlock		      "Scope"
      DstPort		      2
    }
  }
}

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