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📄 mxulie.mdl

📁 m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过
💻 MDL
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		Cell			"MultiInstanceERTCode"
		Cell			"PurelyIntegerCode"
		Cell			"SupportNonFinite"
		Cell			"SupportComplex"
		Cell			"SupportAbsoluteTime"
		Cell			"SupportContinuousTime"
		Cell			"SupportNonInlinedSFcns"
		PropName		"DisabledProps"
	      }
	      Version		      "1.0.4"
	      TargetFcnLib	      "ansi_tfl_tmw.mat"
	      GenFloatMathFcnCalls    "ANSI_C"
	      UtilityFuncGeneration   "Auto"
	      GenerateFullHeader      on
	      GenerateSampleERTMain   off
	      IsPILTarget	      off
	      ModelReferenceCompliant on
	      IncludeMdlTerminateFcn  on
	      CombineOutputUpdateFcns off
	      SuppressErrorStatus     off
	      IncludeFileDelimiter    "Auto"
	      ERTCustomFileBanners    off
	      SupportAbsoluteTime     on
	      LogVarNameModifier      "rt_"
	      MatFileLogging	      on
	      MultiInstanceERTCode    off
	      SupportNonFinite	      on
	      SupportComplex	      on
	      PurelyIntegerCode	      off
	      SupportContinuousTime   on
	      SupportNonInlinedSFcns  on
	      ExtMode		      off
	      ExtModeStaticAlloc      off
	      ExtModeTesting	      off
	      ExtModeStaticAllocSize  1000000
	      ExtModeTransport	      0
	      ExtModeMexFile	      "ext_comm"
	      RTWCAPISignals	      off
	      RTWCAPIParams	      off
	      RTWCAPIStates	      off
	      GenerateASAP2	      off
	    }
	    PropName		    "Components"
	  }
	}
	PropName		"Components"
      }
      Name		      "Configuration"
      SimulationMode	      "normal"
      CurrentDlgPage	      "Solver"
    }
    PropName		    "ConfigurationSets"
  }
  Simulink.ConfigSet {
    $PropName		    "ActiveConfigurationSet"
    $ObjectID		    1
  }
  BlockDefaults {
    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
  }
  BlockParameterDefaults {
    Block {
      BlockType		      Scope
      Floating		      off
      ModelBased	      off
      TickLabels	      "OneTimeTick"
      ZoomMode		      "on"
      Grid		      "on"
      TimeRange		      "auto"
      YMin		      "-5"
      YMax		      "5"
      SaveToWorkspace	      off
      SaveName		      "ScopeData"
      LimitDataPoints	      on
      MaxDataPoints	      "5000"
      Decimation	      "1"
      SampleInput	      off
      SampleTime	      "0"
    }
    Block {
      BlockType		      "S-Function"
      FunctionName	      "system"
      SFunctionModules	      "''"
      PortCounts	      "[]"
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
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    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "mxulie"
    Location		    [76, 115, 922, 678]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "A4"
    PaperUnits		    "centimeters"
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      Reference
      Name		      "Delay"
      Ports		      [1, 1]
      Position		      [125, 410, 170, 460]
      ForegroundColor	      "blue"
      SourceBlock	      "store_alteradspbuilder/Delay"
      SourceType	      "Delay AlteraBlockSet"
      depth		      "1"
      clken		      off
      MaskValue		      "1"
    }
    Block {
      BlockType		      Reference
      Name		      "Delay1"
      Ports		      [1, 1]
      Position		      [535, 410, 580, 460]
      ForegroundColor	      "blue"
      SourceBlock	      "store_alteradspbuilder/Delay"
      SourceType	      "Delay AlteraBlockSet"
      depth		      "1"
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    }
    Block {
      BlockType		      Reference
      Name		      "Delay2"
      Ports		      [1, 1]
      Position		      [270, 410, 315, 460]
      ForegroundColor	      "blue"
      SourceBlock	      "store_alteradspbuilder/Delay"
      SourceType	      "Delay AlteraBlockSet"
      depth		      "1"
      clken		      off
      MaskValue		      "1"
    }
    Block {
      BlockType		      Reference
      Name		      "Delay3"
      Ports		      [1, 1]
      Position		      [450, 410, 495, 460]
      ForegroundColor	      "blue"
      SourceBlock	      "store_alteradspbuilder/Delay"
      SourceType	      "Delay AlteraBlockSet"
      depth		      "1"
      clken		      off
      MaskValue		      "1"
    }
    Block {
      BlockType		      Reference
      Name		      "Delay4"
      Ports		      [1, 1]
      Position		      [360, 410, 405, 460]
      ForegroundColor	      "blue"
      SourceBlock	      "store_alteradspbuilder/Delay"
      SourceType	      "Delay AlteraBlockSet"
      depth		      "1"
      clken		      off
      MaskValue		      "1"
    }
    Block {
      BlockType		      Reference
      Name		      "Logical\nBit Operator"
      Ports		      [2, 1]
      Position		      [175, 238, 245, 287]
      Orientation	      "left"
      ForegroundColor	      "blue"
      NamePlacement	      "alternate"
      SourceBlock	      "gate_alteradspbuilder/Logical\nBit Operator"
      SourceType	      "LogiBit AlteraBlockSet"
      Operator		      "XOR"
      Inputs		      "2"
    }
    Block {
      BlockType		      Reference
      Name		      "NOT"
      Ports		      [1, 1]
      Position		      [45, 427, 85, 443]
      ForegroundColor	      "blue"
      SourceBlock	      "gate_alteradspbuilder/NOT"
      SourceType	      "LogiBit AlteraBlockSet"
      Operator		      "NOT"
      Inputs		      "2"
    }
    Block {
      BlockType		      Reference
      Name		      "NOT1"
      Ports		      [1, 1]
      Position		      [200, 427, 240, 443]
      ForegroundColor	      "blue"
      SourceBlock	      "gate_alteradspbuilder/NOT"
      SourceType	      "LogiBit AlteraBlockSet"
      Operator		      "NOT"
      Inputs		      "2"
    }
    Block {
      BlockType		      Scope
      Name		      "Scope"
      Ports		      [1]
      Position		      [715, 419, 745, 451]
      Location		      [1, 52, 1025, 737]
      Open		      off
      NumInputPorts	      "1"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
      }
      DataFormat	      "StructureWithTime"
    }
    Block {
      BlockType		      Reference
      Name		      "SignalCompiler"
      Ports		      []
      Position		      [234, 38, 303, 85]
      ForegroundColor	      "blue"
      SourceBlock	      "ALTELINK/AltLab/SignalCompiler"
      SourceType	      "SignalCompiler"
      family		      "Stratix"
      opt		      "Speed"
      synthtool		      "Others"
      vstim		      on
      SynthAct		      "None"
      workdir		      "f:\\dspbuilder\\mxulie"
      Procetype		      "prod"
      UseReset		      on
      ResetPin		      "Active High"
      ClockPin		      "Output to Pin"
      ClockPeriod	      "20"
      UseSignalTap	      off
      CreatePtfFile	      off
      SignalTapDepth	      "128"
      VerilogSupport	      off
    }
    Block {
      BlockType		      Reference
      Name		      "mout"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [615, 427, 680, 443]
      ForegroundColor	      "blue"
      SourceBlock	      "bus_alteradspbuilder/AltBus"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Single Bit"
      nodetype		      "Output Port"
      bwl		      "1"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "mout"
      ppat		      "f:\\dspbuilder\\mxulie\\DSPBuilder_mxulie"
      nSgCpl		      "1"
    }
    Line {
      SrcBlock		      "Logical\nBit Operator"
      SrcPort		      1
      Points		      [-150, 0; 0, 170]
      DstBlock		      "NOT"
      DstPort		      1
    }
    Line {
      SrcBlock		      "NOT"
      SrcPort		      1
      DstBlock		      "Delay"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Delay"
      SrcPort		      1
      DstBlock		      "NOT1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "NOT1"
      SrcPort		      1
      DstBlock		      "Delay2"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Delay2"
      SrcPort		      1
      Points		      [10, 0]
      Branch {
	DstBlock		"Delay4"
	DstPort			1
      }
      Branch {
	Points			[0, -160]
	DstBlock		"Logical\nBit Operator"
	DstPort			2
      }
    }
    Line {
      SrcBlock		      "Delay4"
      SrcPort		      1
      DstBlock		      "Delay3"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Delay3"
      SrcPort		      1
      DstBlock		      "Delay1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Delay1"
      SrcPort		      1
      Points		      [10, 0]
      Branch {
	DstBlock		"mout"
	DstPort			1
      }
      Branch {
	Points			[0, -185]
	DstBlock		"Logical\nBit Operator"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "mout"
      SrcPort		      1
      DstBlock		      "Scope"
      DstPort		      1
    }
  }
}

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