📄 fir.mdl
字号:
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType Product
Inputs "2"
Multiplication "Element-wise(.*)"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Zero"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Scope
Floating off
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "0"
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Trigonometry
Operator "sin"
OutputSignalType "auto"
SampleTime "-1"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "fir"
Location [128, 73, 1020, 667]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "Chirp Signal"
Ports [0, 1]
Position [35, 60, 65, 90]
SourceBlock "simulink/Sources/Chirp Signal"
SourceType "chirp"
ShowPortLabels on
f1 "0.1"
T "10"
f2 "1"
VectorParams1D on
}
Block {
BlockType Reference
Name "Delay"
Ports [1, 1]
Position [290, 215, 335, 265]
ForegroundColor "blue"
FontSize 10
SourceBlock "store_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
}
Block {
BlockType Reference
Name "Delay1"
Ports [1, 1]
Position [290, 300, 335, 350]
ForegroundColor "blue"
FontSize 10
SourceBlock "store_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
}
Block {
BlockType Reference
Name "Delay2"
Ports [1, 1]
Position [300, 415, 345, 465]
ForegroundColor "blue"
FontSize 10
SourceBlock "store_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
}
Block {
BlockType Reference
Name "Gain"
Ports [1, 1]
Position [450, 142, 510, 188]
ForegroundColor "blue"
FontSize 10
SourceBlock "arithm_alteradspbuilder/Gain"
SourceType "Gain AlteraBlockSet"
vgain "63"
BusType "Signed Integer"
bwl "8"
bwr "0"
pipeline "0"
lpm off
clken off
MaskValue "1"
gain "63"
}
Block {
BlockType Reference
Name "Gain1"
Ports [1, 1]
Position [450, 217, 510, 263]
ForegroundColor "blue"
FontSize 10
SourceBlock "arithm_alteradspbuilder/Gain"
SourceType "Gain AlteraBlockSet"
vgain "127"
BusType "Signed Integer"
bwl "8"
bwr "0"
pipeline "0"
lpm off
clken off
MaskValue "1"
gain "127"
}
Block {
BlockType Reference
Name "Gain2"
Ports [1, 1]
Position [440, 302, 500, 348]
ForegroundColor "blue"
FontSize 10
SourceBlock "arithm_alteradspbuilder/Gain"
SourceType "Gain AlteraBlockSet"
vgain "127"
BusType "Signed Integer"
bwl "8"
bwr "0"
pipeline "0"
lpm off
clken off
MaskValue "1"
gain "127"
}
Block {
BlockType Reference
Name "Gain3"
Ports [1, 1]
Position [450, 417, 510, 463]
ForegroundColor "blue"
FontSize 10
SourceBlock "arithm_alteradspbuilder/Gain"
SourceType "Gain AlteraBlockSet"
vgain "63"
BusType "Signed Integer"
bwl "8"
bwr "0"
pipeline "0"
lpm off
clken off
MaskValue "1"
gain "63"
}
Block {
BlockType Gain
Name "Gain4"
Position [105, 60, 145, 90]
Gain "127"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Reference
Name "Parallel \nAdder Subtractor"
Ports [4, 1]
Position [585, 257, 620, 333]
ForegroundColor "blue"
FontSize 10
SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Subtra"
"ctor"
SourceType "Sum AlteraBlockSet"
Inputs "4"
direction "++++"
pipeline on
clken off
MaskValue "1"
}
Block {
BlockType Scope
Name "Scope"
Ports [2]
Position [775, 271, 805, 304]
Location [188, 390, 512, 629]
Open off
NumInputPorts "2"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
}
YMin "-5~-5"
YMax "5~5"
DataFormat "StructureWithTime"
}
Block {
BlockType Reference
Name "SignalCompiler"
Ports []
Position [624, 433, 693, 480]
ForegroundColor "blue"
FontSize 10
SourceBlock "ALTELINK/AltLab/SignalCompiler"
SourceType "SignalCompiler"
family "Stratix"
opt "Speed"
synthtool "Others"
vstim on
SynthAct "None"
workdir "F:\\DSPBuilder\\fir"
Procetype "prod"
UseReset on
ResetPin "Active High"
ClockPin "Output to Pin"
ClockPeriod "20"
UseSignalTap off
CreatePtfFile off
SignalTapDepth "128"
VerilogSupport off
}
Block {
BlockType Reference
Name "xin"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [185, 157, 250, 173]
ForegroundColor "blue"
FontSize 10
SourceBlock "bus_alteradspbuilder/AltBus"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "8"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "xin"
ppat "F:\\DSPBuilder\\fir\\DSPBuilder_fir"
nSgCpl "1"
}
Block {
BlockType Reference
Name "yout"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [680, 287, 745, 303]
ForegroundColor "blue"
FontSize 10
SourceBlock "bus_alteradspbuilder/AltBus"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Output Port"
bwl "8"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "yout"
ppat "F:\\DSPBuilder\\fir\\DSPBuilder_fir"
nSgCpl "1"
}
Line {
SrcBlock "xin"
SrcPort 1
Points [0, 0; 10, 0]
Branch {
DstBlock "Gain"
DstPort 1
}
Branch {
Points [0, 75]
DstBlock "Delay"
DstPort 1
}
}
Line {
SrcBlock "Gain"
SrcPort 1
Points [25, 0; 0, 100]
DstBlock "Parallel \nAdder Subtractor"
DstPort 1
}
Line {
SrcBlock "Delay"
SrcPort 1
Points [0, 0; 25, 0]
Branch {
DstBlock "Gain1"
DstPort 1
}
Branch {
Points [0, 50; -100, 0; 0, 35]
DstBlock "Delay1"
DstPort 1
}
}
Line {
SrcBlock "Delay1"
SrcPort 1
Points [0, 0; 20, 0]
Branch {
DstBlock "Gain2"
DstPort 1
}
Branch {
Points [0, 60; -95, 0; 0, 55]
DstBlock "Delay2"
DstPort 1
}
}
Line {
SrcBlock "Delay2"
SrcPort 1
DstBlock "Gain3"
DstPort 1
}
Line {
SrcBlock "Gain1"
SrcPort 1
Points [15, 0; 0, 45]
DstBlock "Parallel \nAdder Subtractor"
DstPort 2
}
Line {
SrcBlock "Gain2"
SrcPort 1
Points [30, 0; 0, -20]
DstBlock "Parallel \nAdder Subtractor"
DstPort 3
}
Line {
SrcBlock "Gain3"
SrcPort 1
Points [25, 0; 0, -115]
DstBlock "Parallel \nAdder Subtractor"
DstPort 4
}
Line {
SrcBlock "Parallel \nAdder Subtractor"
SrcPort 1
DstBlock "yout"
DstPort 1
}
Line {
SrcBlock "Chirp Signal"
SrcPort 1
DstBlock "Gain4"
DstPort 1
}
Line {
SrcBlock "Gain4"
SrcPort 1
Points [10, 0]
Branch {
Points [0, 90]
DstBlock "xin"
DstPort 1
}
Branch {
Points [600, 0]
DstBlock "Scope"
DstPort 1
}
}
Line {
SrcBlock "yout"
SrcPort 1
DstBlock "Scope"
DstPort 2
}
}
}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -