countyubu.v

计数器 同步异步预置数清零 verilog hdl 编写

module countyubu(clk,clr,count,load);
input clk,clr,load;
output[7:0] count;

reg[7:0] count;
always@(posedge clk or negedge clr or negedge load)
begin
  if (!clr)
    count=8'b0;
  else if (!load)
     count=1;
  else count=count+1;
end 
endmodule