anal.out

该代码为配合7号信令模块MK50H27的cpld(xilinx 95144)的逻辑代码,其中包括了VHDL及原理图.

Loading db file 'D:/Fndtn/Synth/lib/libraries/syn/gtech.db'
Reading in the Synopsys vhdl primitives.
E:/SS7/SS7160/MODE1.vhd: