📄 ss7160.rpt
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X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 29/7
Number of signals used by logic mapping into function block: 29
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB7_1 (b)
(unused) 0 0 0 5 FB7_2 79 I/O I
\$I37/iDCounter<0> 2 0 0 3 FB7_3 STD 84 I/O (b)
\$I37/DC2 2 0 0 3 FB7_4 STD 85 I/O I
\$I37/iDCounter<8> 3 0 0 2 FB7_5 STD 82 I/O (b)
SEM_CS 1 0 0 4 FB7_6 STD 86 I/O O
MEM_CS 1 0 0 4 FB7_7 STD 87 I/O O
\$I37/iDCounter<7> 3 0 0 2 FB7_8 STD 88 I/O (b)
\$I37/iDCounter<6> 3 0 0 2 FB7_9 STD 90 I/O (b)
\$I37/iDCounter<5> 3 0 0 2 FB7_10 STD 89 I/O (b)
\$I37/iDCounter<4> 3 0 0 2 FB7_11 STD 92 I/O (b)
\$I37/iDCounter<3> 3 0 0 2 FB7_12 STD 95 I/O (b)
\$I37/iDCounter<2> 3 0 0 2 FB7_13 STD 91 I/O (b)
N_FACE 1 0 0 4 FB7_14 STD 96 I/O O
\$I37/iDCounter<1> 3 0 0 2 FB7_15 STD 97 I/O (b)
\$I37/iCCounter<7> 3 0 0 2 FB7_16 STD 93 I/O (b)
N_ESCE 1 0 0 4 FB7_17 STD 98 I/O O
\$I37/iCCounter<6> 3 0 0 2 FB7_18 STD (b) (b)
Signals Used by Logic in Function Block
1: CPUA13 11: SA19 21: "\$I37/iDCounter<0>".LFBK
2: CPUA14 12: "\$I37/DC2".LFBK 22: "\$I37/iDCounter<1>".LFBK
3: N_CC4 13: "\$I37/iCCounter<0>"
23: "\$I37/iDCounter<2>".LFBK
4: N_CF0 14: "\$I37/iCCounter<1>"
24: "\$I37/iDCounter<3>".LFBK
5: N_DC4 15: "\$I37/iCCounter<2>"
25: "\$I37/iDCounter<4>".LFBK
6: N_DF0 16: "\$I37/iCCounter<3>"
26: "\$I37/iDCounter<5>".LFBK
7: SA15 17: "\$I37/iCCounter<4>"
27: "\$I37/iDCounter<6>".LFBK
8: SA16 18: "\$I37/iCCounter<5>"
28: "\$I37/iDCounter<7>".LFBK
9: SA17 19: "\$I37/iCCounter<6>".LFBK
29: "\$I37/iDCounter<8>".LFBK
10: SA18 20: "\$I37/iCCounter<7>".LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
\$I37/iDCounter<0> ....XX..............X................... 3 3
\$I37/DC2 ....XX.....X............................ 3 3
\$I37/iDCounter<8> ....XX..............XXXXXXXXX........... 11 11
SEM_CS XX...................................... 2 2
MEM_CS XX...................................... 2 2
\$I37/iDCounter<7> ....XX..............XXXXXXXX............ 10 10
\$I37/iDCounter<6> ....XX..............XXXXXXX............. 9 9
\$I37/iDCounter<5> ....XX..............XXXXXX.............. 8 8
\$I37/iDCounter<4> ....XX..............XXXXX............... 7 7
\$I37/iDCounter<3> ....XX..............XXXX................ 6 6
\$I37/iDCounter<2> ....XX..............XXX................. 5 5
N_FACE ......XXXXX............................. 5 5
\$I37/iDCounter<1> ....XX..............XX.................. 4 4
\$I37/iCCounter<7> ..XX........XXXXXXXX.................... 10 10
N_ESCE ......XXXXX............................. 5 5
\$I37/iCCounter<6> ..XX........XXXXXXX..................... 9 9
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 32/4
Number of signals used by logic mapping into function block: 32
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB8_1 (b)
E_RW 1 0 0 4 FB8_2 STD 101 I/O O
(unused) 0 0 0 5 FB8_3 105 I/O I
\$I37/iACounter<0> 2 0 0 3 FB8_4 STD 107 I/O I
\$I37/AC2 2 0 0 3 FB8_5 STD 102 I/O (b)
\$I37/iBCounter<5> 3 0 0 2 FB8_6 STD 103 I/O (b)
\$I37/iACounter<8> 3 0 0 2 FB8_7 STD 109 I/O I
IORDY 0 0 0 5 FB8_8 STD 104 I/O O
\$I37/iACounter<7> 3 0 0 2 FB8_9 STD 106 I/O I
\$I37/iACounter<6> 3 0 0 2 FB8_10 STD 112 I/O I
\$I37/iACounter<5> 3 0 0 2 FB8_11 STD 108 I/O I
\$I37/iACounter<4> 3 0 0 2 FB8_12 STD 111 I/O I
SD3 2 0 0 3 FB8_13 STD 114 I/O I/O
\$I37/iACounter<3> 3 0 0 2 FB8_14 STD 113 I/O (b)
SD2 2 0 0 3 FB8_15 STD 115 I/O I/O
\$I37/iACounter<2> 3 0 0 2 FB8_16 STD 118 I/O I
SD1 2 0 0 3 FB8_17 STD 116 I/O I/O
\$I37/iACounter<1> 3 0 0 2 FB8_18 STD (b) (b)
Signals Used by Logic in Function Block
1: N_AC4 12: SA7 23: "\$I37/iACounter<5>".LFBK
2: N_AF0 13: SA8 24: "\$I37/iACounter<6>".LFBK
3: N_BC4 14: SA9 25: "\$I37/iACounter<7>".LFBK
4: N_BF0 15: SAEN 26: "\$I37/iACounter<8>".LFBK
5: N_BINT 16: SMEMW 27: "\$I37/iBCounter<0>"
6: N_CINT 17: "\$I37/AC2".LFBK 28: "\$I37/iBCounter<1>"
7: N_DINT 18: "\$I37/iACounter<0>".LFBK
29: "\$I37/iBCounter<2>"
8: N_SIOR 19: "\$I37/iACounter<1>".LFBK
30: "\$I37/iBCounter<3>"
9: SA4 20: "\$I37/iACounter<2>".LFBK
31: "\$I37/iBCounter<4>"
10: SA5 21: "\$I37/iACounter<3>".LFBK
32: "\$I37/iBCounter<5>".LFBK
11: SA6 22: "\$I37/iACounter<4>".LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
E_RW ...............X........................ 1 1
\$I37/iACounter<0> XX...............X...................... 3 3
\$I37/AC2 XX..............X....................... 3 3
\$I37/iBCounter<5> ..XX......................XXXXXX........ 8 8
\$I37/iACounter<8> XX...............XXXXXXXXX.............. 11 11
IORDY ........................................ 0 0
\$I37/iACounter<7> XX...............XXXXXXXX............... 10 10
\$I37/iACounter<6> XX...............XXXXXXX................ 9 9
\$I37/iACounter<5> XX...............XXXXXX................. 8 8
\$I37/iACounter<4> XX...............XXXXX.................. 7 7
SD3 ......XXXXXXXXX......................... 9 9
\$I37/iACounter<3> XX...............XXXX................... 6 6
SD2 .....X.XXXXXXXX......................... 9 9
\$I37/iACounter<2> XX...............XXX.................... 5 5
SD1 ....X..XXXXXXXX......................... 9 9
\$I37/iACounter<1> XX...............XX..................... 4 4
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"$OpTx$&_ACS/&_ACS_D2_INV$9__$INT" = /SA7 * /SA6 * /SA5 * /SA4 * /SA3 * SA9 * SA8 *
/SA1 * SA2 * /N_SIOR * N_AHOLD * /"U1/CSE_Q<2>" *
/"U1/CSE_Q<0>" * "U1/CSE_Q<1>"
+ /SA7 * /SA6 * /SA5 * /SA4 * /SA3 * SA9 * SA8 *
/SA1 * SA2 * /N_SIOR * /"U1/CSE_Q<2>" * /"U1/CSE_Q<0>" *
"U1/CSE_Q<1>" * N_AHLDA.LFBK
+ /SA7 * /SA6 * /SA5 * /SA4 * /SA3 * SA9 * SA8 *
/SA1 * SA2 * /N_SIOW * N_AHOLD * /"U1/CSE_Q<2>" *
/"U1/CSE_Q<0>" * "U1/CSE_Q<1>"
+ /SA7 * /SA6 * /SA5 * /SA4 * /SA3 * SA9 * SA8 *
/SA1 * SA2 * /N_SIOW * /"U1/CSE_Q<2>" * /"U1/CSE_Q<0>" *
"U1/CSE_Q<1>" * N_AHLDA.LFBK
"$OpTx$&_BCS/&_BCS_D2_INV$10__$INT" = /SA7 * /SA6 * /SA5 * /SA4 * /SA3 * SA9 * SA8 *
/SA1 * /SA2 * /N_SIOR * N_BHOLD * /"U1/CSE_Q<2>" *
/"U1/CSE_Q<0>" * /"U1/CSE_Q<1>"
+ /SA7 * /SA6 * /SA5 * /SA4 * /SA3 * SA9 * SA8 *
/SA1 * /SA2 * /N_SIOR * /"U1/CSE_Q<2>" * /"U1/CSE_Q<0>" *
/"U1/CSE_Q<1>" * N_BHLDA.LFBK
+ /SA7 * /SA6 * /SA5 * /SA4 * /SA3 * SA9 * SA8 *
/SA1 * /SA2 * /N_SIOW * N_BHOLD * /"U1/CSE_Q<2>" *
/"U1/CSE_Q<0>" * /"U1/CSE_Q<1>"
+ /SA7 * /SA6 * /SA5 * /SA4 * /SA3 * SA9 * SA8 *
/SA1 * /SA2 * /N_SIOW * /"U1/CSE_Q<2>" * /"U1/CSE_Q<0>" *
/"U1/CSE_Q<1>" * N_BHLDA.LFBK
"$OpTx$&_CCS$Q_INV$157" = /SA7 * /SA6 * /SA5 * /SA4 * /SA3 * SA9 * SA8 *
SA1 * SA2 * /N_SIOR * N_CHOLD * /"U1/CSE_Q<2>" *
"U1/CSE_Q<0>" * "U1/CSE_Q<1>"
+ /SA7 * /SA6 * /SA5 * /SA4 * /SA3 * SA9 * SA8 *
SA1 * SA2 * /N_SIOR * /"U1/CSE_Q<2>" * "U1/CSE_Q<0>" *
"U1/CSE_Q<1>" * N_CHLDA.LFBK
+ /SA7 * /SA6 * /SA5 * /SA4 * /SA3 * SA9 * SA8 *
SA1 * SA2 * /N_SIOW * N_CHOLD * /"U1/CSE_Q<2>" *
"U1/CSE_Q<0>" * "U1/CSE_Q<1>"
+ /SA7 * /SA6 * /SA5 * /SA4 * /SA3 * SA9 * SA8 *
SA1 * SA2 * /N_SIOW * /"U1/CSE_Q<2>" * "U1/CSE_Q<0>" *
"U1/CSE_Q<1>" * N_CHLDA.LFBK
"$OpTx$&_DCS$Q_INV$158" = /SA7 * /SA6 * /SA5 * /SA4 * /SA3 * SA9 * SA8 *
SA1 * /SA2 * /N_SIOR * N_DHOLD * /"U1/CSE_Q<2>" *
/"U1/CSE_Q<1>" * "U1/CSE_Q<0>".LFBK
+ /SA7 * /SA6 * /SA5 * /SA4 * /SA3 * SA9 * SA8 *
SA1 * /SA2 * /N_SIOR * /"U1/CSE_Q<2>" * /"U1/CSE_Q<1>" *
"U1/CSE_Q<0>".LFBK * N_DHLDA.PIN
+ /SA7 * /SA6 * /SA5 * /SA4 * /SA3 * SA9 * SA8 *
SA1 * /SA2 * /N_SIOW * N_DHOLD * /"U1/CSE_Q<2>" *
/"U1/CSE_Q<1>" * "U1/CSE_Q<0>".LFBK
+ /SA7 * /SA6 * /SA5 * /SA4 * /SA3 * SA9 * SA8 *
SA1 * /SA2 * /N_SIOW * /"U1/CSE_Q<2>" * /"U1/CSE_Q<1>" *
"U1/CSE_Q<0>".LFBK * N_DHLDA.PIN
/N_ACS = /SA7 * /SA6 * /SA5 * /SA4 * /SA3 * SA9 * SA8 *
/SA1 * SA2 * /N_SIOR * N_AHOLD * /"U1/CSE_Q<2>" *
/"U1/CSE_Q<0>" * "U1/CSE_Q<1>"
+ /SA7 * /SA6 * /SA5 * /SA4 * /SA3 * SA9 * SA8 *
/SA1 * SA2 * /N_SIOR * /"U1/CSE_Q<2>" * /"U1/CSE_Q<0>" *
"U1/CSE_Q<1>" * N_AHLDA.LFBK
+ /SA7 * /SA6 * /SA5 * /SA4 * /SA3 * SA9 * SA8 *
/SA1 * SA2 * /N_SIOW * N_AHOLD * /"U1/CSE_Q<2>" *
/"U1/CSE_Q<0>" * "U1/CSE_Q<1>"
+ /SA7 * /SA6 * /SA5 * /SA4 * /SA3 * SA9 * SA8 *
/SA1 * SA2 * /N_SIOW * /"U1/CSE_Q<2>" * /"U1/CSE_Q<0>" *
"U1/CSE_Q<1>" * N_AHLDA.LFBK
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