ss7160.rpt

该代码为配合7号信令模块MK50H27的cpld(xilinx 95144)的逻辑代码,其中包括了VHDL及原理图.

BREAD                .X........XX............................ 3       3
S_OE                 ............X........................... 1       1
\$I37/iBCounter<7>   ......XX......XXXXXXXX.................. 10      10
LCDLOCK              ...X.X.................................. 2       2
\$I37/iBCounter<6>   ......XX......XXXXXXX................... 9       9
CPUOE                ....X................................... 1       1
\$I37/iBCounter<4>   ......XX......XXXXX..................... 7       7
\$I37/iBCounter<3>   ......XX......XXXX...................... 6       6
\$I37/iBCounter<2>   ......XX......XXX....................... 5       5
\$I37/iBCounter<1>   ......XX......XX........................ 4       4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining:               32/4
Number of signals used by logic mapping into function block:  32
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB4_1         132   I/O     I
(unused)              0       0     0   5     FB4_2         140   I/O     I
\$Net00041_/\$Net00041__CLKF__$INT
                      1       0     0   4     FB4_3   STD   147   I/O     (b)
\$Net00040_/\$Net00040__CLKF__$INT
                      1       0     0   4     FB4_4   STD   149   I/O     (b)
U1/Q<3>/U1/Q<3>_CLKF__$INT
                      1       0     0   4     FB4_5   STD   142   I/O     I
U1/CSE_Q<2>/U1/CSE_Q<2>_CLKF__$INT
                      1       0     0   4     FB4_6   STD   143   I/O     I
N_BSCE                1       0     0   4     FB4_7   STD   150   I/O     O
U1/CSE_Q<0>           2       0     0   3     FB4_8   STD   144   I/O     I
SD0B/SD0B_TRST        2       0     0   3     FB4_9   STD   145   I/O     (b)
N_ASCE                1       0     0   4     FB4_10  STD   151   I/O     O
SD0B$WA0              2       0     0   3     FB4_11  STD   146   I/O     I
$OpTx$&_DCS$Q_INV$158
                      4       0     0   1     FB4_12  STD   148   I/O     I
N_CSCE                1       0     0   4     FB4_13  STD   153   I/O     O
N_DSCE                1       0     0   4     FB4_14  STD   152   I/O     O
N_DOE                 1       0     0   4     FB4_15  STD   154   I/O     O
N_COE                 1       0     0   4     FB4_16  STD   155   I/O     O
DR_W                  1       0     0   4     FB4_17  STD   156   I/O     O
SD0B$WA1              5       0     0   0     FB4_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: CREAD             12: N_SIOW            23: SA6 
  2: DREAD             13: SA1               24: SA7 
  3: N_AHLDA           14: SA15              25: SA8 
  4: N_AINT            15: SA16              26: SA9 
  5: N_BHLDA           16: SA17              27: SAEN 
  6: N_CDAS            17: SA18              28: SD0 
  7: N_CHLDA           18: SA19              29: "U1/CSE_Q<0>".LFBK 
  8: N_DDAS            19: SA2               30: "U1/CSE_Q<1>" 
  9: N_DHLDA           20: SA3               31: "U1/CSE_Q<2>" 
 10: N_DHOLD           21: SA4               32: "U1/CSE_Q<2>/U1/CSE_Q<2>_CLKF__$INT".LFBK 
 11: N_SIOR            22: SA5              

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
\$Net00041_/\$Net00041__CLKF__$INT 
                     ...........X........XXXXXXX............. 8       8
\$Net00040_/\$Net00040__CLKF__$INT 
                     ...........X........XXXXXXX............. 8       8
U1/Q<3>/U1/Q<3>_CLKF__$INT 
                     ...........X........XXXXXXX............. 8       8
U1/CSE_Q<2>/U1/CSE_Q<2>_CLKF__$INT 
                     ...........X.......XXXXXXXX............. 9       9
N_BSCE               .............XXXXX..........XXX......... 8       8
U1/CSE_Q<0>          ...........................X...X........ 2       2
SD0B/SD0B_TRST       ..........X........XXXXXXXX...X......... 10      10
N_ASCE               .............XXXXX..........XXX......... 8       8
SD0B$WA0             ...X......X.........XXXXXXX............. 9       9
$OpTx$&_DCS$Q_INV$158 
                     ........XXXXX.....XXXXXXXX..XXX......... 16      16
N_CSCE               .............XXXXX..........XXX......... 8       8
N_DSCE               .............XXXXX..........XXX......... 8       8
N_DOE                .X.....X................................ 2       2
N_COE                X....X.................................. 2       2
DR_W                 .X.....X................................ 2       2
SD0B$WA1             ..X.X.X.X.X........XXXXXXX..XXX......... 15      15
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB5 ***********************************
Number of function block inputs used/remaining:               16/20
Number of signals used by logic mapping into function block:  16
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
LED0                  2       0     0   3     FB5_1   STD   65    I/O     O
(unused)              0       0     0   5     FB5_2         58    I/O     
LED1                  2       0     0   3     FB5_3   STD   66    I/O     O
LED2                  2       0     0   3     FB5_4   STD   67    I/O     O
(unused)              0       0     0   5     FB5_5         59    I/O     
U1/Q<3>               2       0     0   3     FB5_6   STD   60    I/O     (b)
U1/Q<2>               2       0     0   3     FB5_7   STD   74    I/O     (b)
U1/Q<1>               2       0     0   3     FB5_8   STD   62    I/O     I
U1/Q<0>               2       0     0   3     FB5_9   STD   63    I/O     (b)
U1/CSE_Q<2>           2       0     0   3     FB5_10  STD   76    I/O     (b)
RUN                   2       0     0   3     FB5_11  STD   64    I/O     O
LED3                  2       0     0   3     FB5_12  STD   68    I/O     O
U1/CSE_Q<1>           2       0     0   3     FB5_13  STD   78    I/O     I
\$I37/iCCounter<5>    3       0     0   2     FB5_14  STD   69    I/O     (b)
\$I37/iCCounter<4>    3       0     0   2     FB5_15  STD   72    I/O     (b)
\$I37/iCCounter<3>    3       0     0   2     FB5_16  STD   83    I/O     (b)
\$I37/iCCounter<2>    3       0     0   2     FB5_17  STD   77    I/O     (b)
\$I37/iCCounter<1>    3       0     0   2     FB5_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: N_CC4              7: "U1/CSE_Q<2>/U1/CSE_Q<2>_CLKF__$INT" 
                                             12: "\$I37/iCCounter<3>".LFBK 
  2: N_CF0              8: "U1/Q<3>/U1/Q<3>_CLKF__$INT" 
                                             13: "\$I37/iCCounter<4>".LFBK 
  3: SD0                9: "\$I37/iCCounter<0>" 
                                             14: "\$I37/iCCounter<5>".LFBK 
  4: SD1               10: "\$I37/iCCounter<1>".LFBK 
                                             15: "\$Net00040_/\$Net00040__CLKF__$INT" 
  5: SD2               11: "\$I37/iCCounter<2>".LFBK 
                                             16: "\$Net00041_/\$Net00041__CLKF__$INT" 
  6: SD3              

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
LED0                 ..X...........X......................... 2       2
LED1                 ...X..........X......................... 2       2
LED2                 ....X.........X......................... 2       2
U1/Q<3>              .....X.X................................ 2       2
U1/Q<2>              ....X..X................................ 2       2
U1/Q<1>              ...X...X................................ 2       2
U1/Q<0>              ..X....X................................ 2       2
U1/CSE_Q<2>          ....X.X................................. 2       2
RUN                  ..X............X........................ 2       2
LED3                 .....X........X......................... 2       2
U1/CSE_Q<1>          ...X..X................................. 2       2
\$I37/iCCounter<5>   XX......XXXXXX.......................... 8       8
\$I37/iCCounter<4>   XX......XXXXX........................... 7       7
\$I37/iCCounter<3>   XX......XXXX............................ 6       6
\$I37/iCCounter<2>   XX......XXX............................. 5       5
\$I37/iCCounter<1>   XX......XX.............................. 4       4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB6 ***********************************
Number of function block inputs used/remaining:               7/29
Number of signals used by logic mapping into function block:  7
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB6_1               (b)     
SD0                   2       0     0   3     FB6_2   STD   117   I/O     I/O
(unused)              0       0     0   5     FB6_3         119   I/O     I
(unused)              0       0     0   5     FB6_4         123   I/O     I
(unused)              0       0     0   5     FB6_5         122   I/O     
(unused)              0       0     0   5     FB6_6         124   I/O     I
(unused)              0       0     0   5     FB6_7         125   I/O     I
(unused)              0       0     0   5     FB6_8         126   I/O     I
(unused)              0       0     0   5     FB6_9         129   I/O     I
(unused)              0       0     0   5     FB6_10        128   I/O     I
(unused)              0       0     0   5     FB6_11        133   I/O     I
(unused)              0       0     0   5     FB6_12        134   I/O     
(unused)              0       0     0   5     FB6_13        130   I/O     I
(unused)              0       0     0   5     FB6_14        135   I/O     
(unused)              0       0     0   5     FB6_15        138   I/O     I
(unused)              0       0     0   5     FB6_16        131   I/O     I
\$I37/iCCounter<0>    2       0     0   3     FB6_17  STD   139   I/O     I
\$I37/CC2             2       0     0   3     FB6_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: N_CC4              4: "SD0B$WA1"         6: "\$I37/CC2".LFBK 
  2: N_CF0              5: "SD0B/SD0B_TRST"   7: "\$I37/iCCounter<0>".LFBK 
  3: "SD0B$WA0"       

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
SD0                  ..XXX................................... 3       3
\$I37/iCCounter<0>   XX....X................................. 3       3
\$I37/CC2            XX...X.................................. 3       3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell