devider.par_nlf

本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.

Release 6.2.01i - netgen G.29
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

Loading device database for application netgen from file "devider.ncd".
   "devider" is an NCD, version 2.38, device xc2s200, package pq208, speed -5
Loading device for application netgen from file 'v200.nph' in environment
C:/Xilinx.
Loading constraints from file "devider.pcf"...
  Flattening design ...
  Flattening design completed.
  Specializing design ...
  Specializing design completed.
  Preping physical only global signals ...
  Preping design's networks ...
  Preping design's macros ...
Writing VHDL netlist devider_timesim.vhd ...
Writing VHDL SDF file devider_timesim.sdf ...
Total memory usage is 51764 kilobytes