devider.syr

本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.

Release 6.2i - xst G.29
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: devider.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : devider.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : devider
Output Format                      : NGC
Target Device                      : xc2s200-5-pq208

---- Source Options
Top Module Name                    : devider
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : devider.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file d:/fpga/仿真/divider/devider.vhdl in Library work.
Entity <devider> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <devider> (Architecture <Behavioral>).
Entity <devider> analyzed. Unit <devider> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <devider>.
    Related source file is d:/fpga/仿真/divider/devider.vhdl.
    Found 7-bit comparator greatequal for signal <$n0005> created at line 33.
    Found 6-bit comparator greatequal for signal <$n0006> created at line 40.
    Found 5-bit comparator greatequal for signal <$n0007> created at line 47.
    Found 4-bit comparator greatequal for signal <$n0008> created at line 55.
    Found 4-bit subtractor for signal <$n0009> created at line 57.
    Found 4-bit subtractor for signal <$n0010> created at line 35.
    Found 4-bit subtractor for signal <$n0011> created at line 42.
    Found 4-bit subtractor for signal <$n0012> created at line 49.
    Found 16 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   4 Adder/Subtracter(s).
	inferred   4 Comparator(s).
	inferred  16 Multiplexer(s).
Unit <devider> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 4
 4-bit subtractor                  : 4
# Comparators                      : 4
 4-bit comparator greatequal       : 1
 5-bit comparator greatequal       : 1
 6-bit comparator greatequal       : 1
 7-bit comparator greatequal       : 1
# Multiplexers                     : 4
 4-bit 2-to-1 multiplexer          : 4

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <devider> ...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block devider, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : devider.ngr
Top Level Output File Name         : devider
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 17

Macro Statistics :
# Multiplexers                     : 4
#      2-to-1 multiplexer          : 4
# Adders/Subtractors               : 4
#      4-bit subtractor            : 4
# Comparators                      : 4
#      4-bit comparator greatequal : 1
#      5-bit comparator greatequal : 1
#      6-bit comparator greatequal : 1
#      7-bit comparator greatequal : 1

Cell Usage :
# BELS                             : 95
#      GND                         : 1
#      LUT1                        : 12
#      LUT2                        : 3
#      LUT3                        : 15
#      LUT4                        : 23
#      MUXCY                       : 24
#      VCC                         : 1
#      XORCY                       : 16
# IO Buffers                       : 17
#      IBUF                        : 8
#      OBUF                        : 9
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200pq208-5 

 Number of Slices:                      32  out of   2352     1%  
 Number of 4 input LUTs:                53  out of   4704     1%  
 Number of bonded IOBs:                 17  out of    144    11%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 28.646ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               28.646ns (Levels of Logic = 18)
  Source:            b<0> (PAD)
  Destination:       y<0> (PAD)

  Data Path: b<0> to y<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             9   0.924   2.120  b_0_IBUF (b_0_IBUF)
     LUT2:I0->O            1   0.653   0.000  Mcompar__n0005_inst_lut2_31 (Mcompar__n0005_inst_lut2_3)
     MUXCY:S->O            1   0.784   0.000  Mcompar__n0005_inst_cy_3 (Mcompar__n0005_inst_cy_3)
     MUXCY:CI->O           1   0.050   0.000  Mcompar__n0005_inst_cy_4 (Mcompar__n0005_inst_cy_4)
     MUXCY:CI->O           1   0.050   0.000  Mcompar__n0005_inst_cy_5 (Mcompar__n0005_inst_cy_5)
     MUXCY:CI->O          11   0.050   2.300  Mcompar__n0005_inst_cy_6 (Mcompar__n0005_inst_cy_6)
     LUT3:I0->O            3   0.653   1.480  Mmux__n0000_Result<1>1 (_n0019<1>)
     MUXCY:DI->O           1   0.316   0.000  Msub__n0011_inst_cy_19 (Msub__n0011_inst_cy_19)
     MUXCY:CI->O           0   0.050   0.000  Msub__n0011_inst_cy_20 (Msub__n0011_inst_cy_20)
     XORCY:CI->O           3   0.500   1.480  Msub__n0011_inst_sum_3 (_n0015<7>)
     LUT4:I1->O            1   0.653   0.000  Mcompar__n0007_inst_lut2_161 (Mcompar__n0007_inst_lut2_16)
     MUXCY:S->O            1   0.784   0.000  Mcompar__n0007_inst_cy_16 (Mcompar__n0007_inst_cy_16)
     MUXCY:CI->O          10   0.050   2.200  Mcompar__n0007_inst_cy_17 (Mcompar__n0007_inst_cy_17)
     LUT3:I0->O            2   0.653   1.340  Mmux__n0002_Result<0>1 (_n0013<0>)
     LUT4:I2->O            1   0.653   1.150  Mcompar__n0008_AGEB24 (CHOICE9)
     LUT4:I2->O            5   0.653   1.740  Mcompar__n0008_AGEB42 (CHOICE13)
     LUT2:I0->O            1   0.653   1.150  Mcompar__n0008_AGEB75 (y_0_OBUF)
     OBUF:I->O                 5.557          y_0_OBUF (y<0>)
    ----------------------------------------
    Total                     28.646ns (13.686ns logic, 14.960ns route)
                                       (47.8% logic, 52.2% route)

=========================================================================
CPU : 4.36 / 6.22 s | Elapsed : 4.00 / 6.00 s
 
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Total memory usage is 60044 kilobytes