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Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file d:/fpga/仿真/divider/devider.vhdl in Library work.Entity <devider> (Architecture <Behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <devider> (Architecture <Behavioral>).Entity <devider> analyzed. Unit <devider> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <devider>. Related source file is d:/fpga/仿真/divider/devider.vhdl. Found 7-bit comparator greatequal for signal <$n0005> created at line 33. Found 6-bit comparator greatequal for signal <$n0006> created at line 40. Found 5-bit comparator greatequal for signal <$n0007> created at line 47. Found 4-bit comparator greatequal for signal <$n0008> created at line 55. Found 4-bit subtractor for signal <$n0009> created at line 57. Found 4-bit subtractor for signal <$n0010> created at line 35. Found 4-bit subtractor for signal <$n0011> created at line 42. Found 4-bit subtractor for signal <$n0012> created at line 49. Found 16 1-bit 2-to-1 multiplexers. Summary: inferred 4 Adder/Subtracter(s). inferred 4 Comparator(s). inferred 16 Multiplexer(s).Unit <devider> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Adders/Subtractors : 4 4-bit subtractor : 4# Comparators : 4 4-bit comparator greatequal : 1 5-bit comparator greatequal : 1 6-bit comparator greatequal : 1 7-bit comparator greatequal : 1# Multiplexers : 4 4-bit 2-to-1 multiplexer : 4==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <devider> ...Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block devider, actual ratio is 1.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s200pq208-5 Number of Slices: 32 out of 2352 1% Number of 4 input LUTs: 53 out of 4704 1% Number of bonded IOBs: 17 out of 144 11% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 28.646ns=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file d:/fpga/仿真/divider/compact_divider.vhdl in Library work.ERROR:HDLParsers:3312 - d:/fpga/仿真/divider/compact_divider.vhdl Line 34. Undefined symbol 'n'.ERROR:HDLParsers:1209 - d:/fpga/仿真/divider/compact_divider.vhdl Line 34. n: Undefined symbol (last report in this block)ERROR:HDLParsers:3312 - d:/fpga/仿真/divider/compact_divider.vhdl Line 35. Undefined symbol 'temp'.ERROR:HDLParsers:1209 - d:/fpga/仿真/divider/compact_divider.vhdl Line 35. temp: Undefined symbol (last report in this block)ERROR:HDLParsers:3312 - d:/fpga/仿真/divider/compact_divider.vhdl Line 35. Undefined symbol 'i'.ERROR:HDLParsers:1209 - d:/fpga/仿真/divider/compact_divider.vhdl Line 35. i: Undefined symbol (last report in this block)--> Total memory usage is 48220 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file d:/fpga/仿真/divider/compact_divider.vhdl in Library work.ERROR:HDLParsers:3312 - d:/fpga/仿真/divider/compact_divider.vhdl Line 34. Undefined symbol 'n'.ERROR:HDLParsers:1209 - d:/fpga/仿真/divider/compact_divider.vhdl Line 34. n: Undefined symbol (last report in this block)ERROR:HDLParsers:3312 - d:/fpga/仿真/divider/compact_divider.vhdl Line 35. Undefined symbol 'i'.ERROR:HDLParsers:1209 - d:/fpga/仿真/divider/compact_divider.vhdl Line 35. i: Undefined symbol (last report in this block)--> Total memory usage is 48220 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file d:/fpga/仿真/divider/compact_divider.vhdl in Library work.Entity <compact_divider> (Architecture <Behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <compact_divider> (Architecture <Behavioral>).Entity <compact_divider> analyzed. Unit <compact_divider> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <compact_divider>. Related source file is d:/fpga/仿真/divider/compact_divider.vhdl. Found 7-bit comparator greatequal for signal <$n0005> created at line 36. Found 6-bit comparator greatequal for signal <$n0006> created at line 36. Found 5-bit comparator greatequal for signal <$n0007> created at line 36. Found 4-bit comparator greatequal for signal <$n0008> created at line 36. Found 4-bit subtractor for signal <$n0009> created at line 38. Found 4-bit subtractor for signal <$n0010> created at line 38. Found 4-bit subtractor for signal <$n0011> created at line 38. Found 4-bit subtractor for signal <$n0012> created at line 38. Found 16 1-bit 2-to-1 multiplexers. Summary: inferred 4 Adder/Subtracter(s). inferred 4 Comparator(s). inferred 16 Multiplexer(s).Unit <compact_divider> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Adders/Subtractors : 4 4-bit subtractor : 4# Comparators : 4 4-bit comparator greatequal : 1 5-bit comparator greatequal : 1 6-bit comparator greatequal : 1 7-bit comparator greatequal : 1# Multiplexers : 4 4-bit 2-to-1 multiplexer : 4==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <compact_divider> ...Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block compact_divider, actual ratio is 1.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s200pq208-5 Number of Slices: 32 out of 2352 1% Number of 4 input LUTs: 53 out of 4704 1% Number of bonded IOBs: 17 out of 144 11% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 28.646ns=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd d:\fpga\仿真\divider_定点除法器/_ngo -i-p xc2s200-pq208-5 compact_divider.ngc compact_divider.ngd Reading NGO file "D:/FPGA/仿真/Divider_定点除法器/compact_divider.ngc" ...Reading component libraries for design expansion...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 39140 kilobytesWriting NGD file "compact_divider.ngd" ...Writing NGDBUILD log file "compact_divider.bld"...NGDBUILD done.Completed process "Translate".
Started process "Map".Using target part "2s200pq208-5".Removing unused or disabled logic...Running cover...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors: 0Number of warnings: 0Logic Utilization: Number of 4 input LUTs: 50 out of 4,704 1%Logic Distribution: Number of occupied Slices: 28 out of 2,352 1% Number of Slices containing only related logic: 28 out of 28 100% Number of Slices containing unrelated logic: 0 out of 28 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 56 out of 4,704 1% Number used as logic: 50 Number used as a route-thru: 6 Number of bonded IOBs: 17 out of 140 12%Total equivalent gate count for design: 420Additional JTAG gate count for IOBs: 816Peak Memory Usage: 63 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Mapping completed.See MAP report file "compact_divider_map.mrp" for details.Completed process "Map".Mapping Module compact_divider . . .
MAP command line:
map -intstyle ise -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o compact_divider_map.ncd compact_divider.ngd compact_divider.pcf
Mapping Module compact_divider: DONE
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