📄 devider.par
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Release 6.2i Par G.29Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.LIJINTAO-452B0A:: Thu Jul 13 10:57:52 2006C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 devider_map.ncd
devider.ncd devider.pcf Constraints file: devider.pcfLoading device database for application Par from file "devider_map.ncd". "devider" is an NCD, version 2.38, device xc2s200, package pq208, speed -5Loading device for application Par from file 'v200.nph' in environment
C:/Xilinx.Device speed data version: PRODUCTION 1.27 2003-12-13.Device utilization summary: Number of External IOBs 17 out of 140 12% Number of LOCed External IOBs 0 out of 17 0% Number of SLICEs 28 out of 2352 1%Overall effort level (-ol): Standard (set by user)Placer effort level (-pl): Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl): Standard (set by user)Phase 1.1Phase 1.1 (Checksum:9896f1) REAL time: 0 secs Phase 2.23Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs Phase 3.3Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8.Phase 5.8 (Checksum:99b181) REAL time: 0 secs Phase 6.5Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file devider.ncd.Total REAL time to Placer completion: 2 secs Total CPU time to Placer completion: 1 secs Phase 1: 183 unrouted; REAL time: 2 secs Phase 2: 183 unrouted; REAL time: 2 secs Phase 3: 36 unrouted; REAL time: 2 secs Phase 4: 0 unrouted; REAL time: 2 secs Total REAL time to Router completion: 2 secs Total CPU time to Router completion: 1 secs Generating "par" statistics. The Delay Summary Report The SCORE FOR THIS DESIGN is: 272The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0 The AVERAGE CONNECTION DELAY for this design is: 1.894 The MAXIMUM PIN DELAY IS: 5.614 The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 4.147 Listing Pin Delays by value: (nsec) d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 6.00 d >= 6.00 --------- --------- --------- --------- --------- --------- 57 61 23 11 31 0Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 2 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 53 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Writing design to file devider.ncd.PAR done.
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