devider.vhdl

来自「本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.」· VHDL 代码 · 共 65 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity devider is
port(
      a,b:in integer range 0 to 15;
	 y:out std_logic_vector(3 downto 0);
	 rest:out integer range 0 to 15;
	 err:out std_logic
	 );
end devider;

architecture Behavioral of devider is

begin
process(a,b)
  variable  temp1:integer range 0 to 15;
  variable  temp2:integer range 0 to 15;
  begin
  temp1:=a;
  temp2:=b;
  if b=0 then err<='1';
  else  err<='0';
  end if;

  if temp1>=temp2*8 then
  y(3)<='1';
  temp1:=temp1-temp2*8;
  else
  y(3)<='0';
  end if;

  if temp1>=temp2*4 then
  y(2)<='1';
  temp1:=temp1-temp2*4;
  else
  y(2)<='0';
  end if;

   if temp1>=temp2*2 then
  y(1)<='1';
  temp1:=temp1-temp2*2;
  else
  y(1)<='0';
  end if;


   if temp1>=temp2 then
  y(0)<='1';
  temp1:=temp1-temp2;
  else
  y(0)<='0';
  end if;

  rest<=temp1;
  end process;
end Behavioral;