compact_divider.vhdl

本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity compact_divider is
--generic(n:integer :=3);
port(
      a,b:in integer range 0 to 15;
	 y:out std_logic_vector(3 downto 0);
	 rest:out integer range 0 to 15;
	 err:out std_logic
	 );

end compact_divider;

architecture Behavioral of compact_divider is

begin
process(a,b)
  variable  temp1:integer range 0 to 15;
  variable  temp2:integer range 0 to 15;
  begin
  temp1:=a;
  temp2:=b;
  if b=0 then err<='1';
  else  err<='0';
  end if;

 for i in 3 downto 0 loop	 --n
    if  temp1>=temp2*2**i then
         y(i)<='1';
	    temp1:=temp1-temp2*2**i;
     else
	    y(i)<='0';
     end if;
	end loop;
	 rest<=temp1;
end process;

end Behavioral;