divider.gfl

本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.

# XST (Creating Lso File) : 
devider.lso
# xst flow : RunXST
devider.syr
devider.prj
devider.sprj
devider.ana
devider.stx
devider.cmd_log
devider.ngc
devider.ngr
# XST (Creating Lso File) : 
compact_divider.lso
# xst flow : RunXST
compact_divider.syr
compact_divider.prj
compact_divider.sprj
compact_divider.ana
compact_divider.stx
compact_divider.cmd_log
# XST (Creating Lso File) : 
compact_divider.lso
# xst flow : RunXST
compact_divider.syr
compact_divider.prj
compact_divider.sprj
compact_divider.ana
compact_divider.stx
compact_divider.cmd_log
# XST (Creating Lso File) : 
compact_divider.lso
# xst flow : RunXST
compact_divider.syr
compact_divider.prj
compact_divider.sprj
compact_divider.ana
compact_divider.stx
compact_divider.cmd_log
compact_divider.ngc
compact_divider.ngr
# ProjNav -> New Source -> TBW
d:\fpga\仿真\divider\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
t_compact.vhw
t_compact.ano
t_compact.tfw
# ModelSim : Simulate Behavioral VHDL Model
t_compact.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ProjNav -> New Source -> TBW
d:\fpga\仿真\divider\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
t_divider.vhw
t_divider.ano
t_divider.tfw
# ModelSim : Simulate Behavioral VHDL Model
t_divider.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\fpga\仿真\divider_定点除法器/_ngo
compact_divider.ngd
compact_divider_ngdbuild.nav
compact_divider.bld
.untf
compact_divider.cmd_log
# Implementation : Map
compact_divider_map.ncd
compact_divider.ngm
compact_divider.pcf
compact_divider.nc1
compact_divider.mrp
compact_divider_map.mrp
compact_divider.mdf
__projnav/map.log
compact_divider.cmd_log
MAP_NO_GUIDE_FILE_CPF "compact_divider"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
compact_divider.twr
compact_divider.twx
compact_divider.tsi
compact_divider.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
compact_divider.ncd
compact_divider.par
compact_divider.pad
compact_divider_pad.txt
compact_divider_pad.csv
compact_divider.pad_txt
compact_divider.dly
reportgen.log
compact_divider.xpi
compact_divider.grf
compact_divider.itr
compact_divider_last_par.ncd
__projnav/par.log
compact_divider.placed_ncd_tracker
compact_divider.routed_ncd_tracker
compact_divider.cmd_log
PAR_NO_GUIDE_FILE_CPF "compact_divider"
# Implementation : Generate Post-Par Simulation Model
compact_divider_timesim.vhd
compact_divider_timesim.sdf
compact_divider_timesim.sdf
compact_divider_timesim.vhd
compact_divider_timesim.nlf
compact_divider.par_nlf
compact_divider.vhdsim_par
compact_divider.cmd_log
__projnav/netgen_par_tcl.rsp
# Simulation :Simulate Post-Place & Route VHDL Model
t_compact.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
t_compact.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\fpga\仿真\divider_定点除法器/_ngo
devider.ngd
devider_ngdbuild.nav
devider.bld
.untf
devider.cmd_log
# Implementation : Map
devider_map.ncd
devider.ngm
devider.pcf
devider.nc1
devider.mrp
devider_map.mrp
devider.mdf
__projnav/map.log
devider.cmd_log
MAP_NO_GUIDE_FILE_CPF "devider"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
devider.twr
devider.twx
devider.tsi
devider.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
devider.ncd
devider.par
devider.pad
devider_pad.txt
devider_pad.csv
devider.pad_txt
devider.dly
reportgen.log
devider.xpi
devider.grf
devider.itr
devider_last_par.ncd
__projnav/par.log
devider.placed_ncd_tracker
devider.routed_ncd_tracker
devider.cmd_log
PAR_NO_GUIDE_FILE_CPF "devider"
# Implementation : Generate Post-Par Simulation Model
devider_timesim.vhd
devider_timesim.sdf
devider_timesim.sdf
devider_timesim.vhd
devider_timesim.nlf
devider.par_nlf
devider.vhdsim_par
devider.cmd_log
__projnav/netgen_par_tcl.rsp
# Simulation :Simulate Post-Place & Route VHDL Model
t_divider.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
t_divider.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
t_divider.vhw
t_divider.ano
t_divider.tfw
# ModelSim : Simulate Behavioral VHDL Model
t_divider.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf