hdpdeps.ref

本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.

V1 8
FL d:/fpga/仿真/divider/compact_divider.vhdl 2006/05/29.11:39:19
FL D:/FPGA/仿真/Divider_定点除法器/compact_divider.vhdl 2006/05/29.11:39:19
EN work/COMPACT_DIVIDER FL D:/FPGA/仿真/Divider_定点除法器/compact_divider.vhdl \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/COMPACT_DIVIDER/BEHAVIORAL \
      FL D:/FPGA/仿真/Divider_定点除法器/compact_divider.vhdl \
      EN work/COMPACT_DIVIDER
FL d:/fpga/仿真/divider/devider.vhdl 2006/05/29.11:33:51
FL D:/FPGA/仿真/Divider_定点除法器/devider.vhdl 2006/05/29.11:33:51
EN work/DEVIDER         FL D:/FPGA/仿真/Divider_定点除法器/devider.vhdl \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/DEVIDER/BEHAVIORAL FL D:/FPGA/仿真/Divider_定点除法器/devider.vhdl \
      EN work/DEVIDER