devider_timesim.vhd

本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.

    );
  Msub_n0011_inst_cy_18_68 : X_MUX2
    port map (
      IA => Q_n0019(0),
      IB => Q_n0015_4_CYINIT,
      SEL => Msub_n0011_inst_lut2_18,
      O => Msub_n0011_inst_cy_18
    );
  Msub_n0011_inst_sum_0 : X_XOR2
    port map (
      I0 => Q_n0015_4_CYINIT,
      I1 => Msub_n0011_inst_lut2_18,
      O => Q_n0015_4_XORF
    );
  Msub_n0011_inst_lut2_1811 : X_LUT4
    generic map(
      INIT => X"0C3F"
    )
    port map (
      ADR0 => Q_n0019(0),
      ADR1 => Mcompar_n0005_inst_cy_6,
      ADR2 => a_0_IBUF,
      ADR3 => Q_n0014(4),
      O => Msub_n0011_inst_lut2_18
    );
  Msub_n0011_inst_lut2_1911 : X_LUT4
    generic map(
      INIT => X"330F"
    )
    port map (
      ADR0 => Q_n0019(1),
      ADR1 => a_1_IBUF,
      ADR2 => Q_n0014(5),
      ADR3 => Mcompar_n0005_inst_cy_6,
      O => Msub_n0011_inst_lut2_19
    );
  Q_n0015_4_COUTUSED : X_BUF
    port map (
      I => Q_n0015_4_CYMUXG,
      O => Msub_n0011_inst_cy_19
    );
  Q_n0015_4_XUSED : X_BUF
    port map (
      I => Q_n0015_4_XORF,
      O => Q_n0015(4)
    );
  Q_n0015_4_YUSED : X_BUF
    port map (
      I => Q_n0015_4_XORG,
      O => Q_n0015(5)
    );
  Msub_n0011_inst_cy_19_69 : X_MUX2
    port map (
      IA => Q_n0019(1),
      IB => Msub_n0011_inst_cy_18,
      SEL => Msub_n0011_inst_lut2_19,
      O => Q_n0015_4_CYMUXG
    );
  Msub_n0011_inst_sum_1 : X_XOR2
    port map (
      I0 => Msub_n0011_inst_cy_18,
      I1 => Msub_n0011_inst_lut2_19,
      O => Q_n0015_4_XORG
    );
  Q_n0015_4_CYINIT_70 : X_BUF
    port map (
      I => Q_n0015_4_LOGIC_ONE,
      O => Q_n0015_4_CYINIT
    );
  Msub_n0011_inst_cy_20_71 : X_MUX2
    port map (
      IA => Q_n0019(2),
      IB => Q_n0015_6_CYINIT,
      SEL => Q_n0015_6_FROM,
      O => Msub_n0011_inst_cy_20
    );
  Msub_n0011_inst_sum_2 : X_XOR2
    port map (
      I0 => Q_n0015_6_CYINIT,
      I1 => Q_n0015_6_FROM,
      O => Q_n0015_6_XORF
    );
  Q_n0015_6_F : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => Q_n0019(2),
      ADR1 => VCC,
      ADR2 => Msub_n0011_inst_lut2_20,
      ADR3 => VCC,
      O => Q_n0015_6_FROM
    );
  Msub_n0011_inst_lut2_211 : X_LUT4
    generic map(
      INIT => X"E41B"
    )
    port map (
      ADR0 => Mcompar_n0005_inst_cy_6,
      ADR1 => Q_n0014(7),
      ADR2 => a_3_IBUF,
      ADR3 => b_1_IBUF,
      O => Msub_n0011_inst_lut2_21
    );
  Q_n0015_6_XUSED : X_BUF
    port map (
      I => Q_n0015_6_XORF,
      O => Q_n0015(6)
    );
  Q_n0015_6_YUSED : X_BUF
    port map (
      I => Q_n0015_6_XORG,
      O => Q_n0015(7)
    );
  Msub_n0011_inst_sum_3 : X_XOR2
    port map (
      I0 => Msub_n0011_inst_cy_20,
      I1 => Msub_n0011_inst_lut2_21,
      O => Q_n0015_6_XORG
    );
  Q_n0015_6_CYINIT_72 : X_BUF
    port map (
      I => Msub_n0011_inst_cy_19,
      O => Q_n0015_6_CYINIT
    );
  Msub_n0012_inst_lut2_201 : X_LUT4
    generic map(
      INIT => X"CA35"
    )
    port map (
      ADR0 => Q_n0015(6),
      ADR1 => Q_n0019(2),
      ADR2 => Mcompar_n0006_inst_cy_12,
      ADR3 => b_1_IBUF,
      O => Msub_n0012_inst_lut2_20_FROM
    );
  Msub_n0009_inst_lut2_191 : X_LUT4
    generic map(
      INIT => X"E14B"
    )
    port map (
      ADR0 => Mcompar_n0007_inst_cy_17,
      ADR1 => Q_n0016(5),
      ADR2 => b_1_IBUF,
      ADR3 => Q_n0021(1),
      O => Msub_n0012_inst_lut2_20_GROM
    );
  Msub_n0012_inst_lut2_20_XUSED : X_BUF
    port map (
      I => Msub_n0012_inst_lut2_20_FROM,
      O => Msub_n0012_inst_lut2_20
    );
  Msub_n0012_inst_lut2_20_YUSED : X_BUF
    port map (
      I => Msub_n0012_inst_lut2_20_GROM,
      O => Msub_n0009_inst_lut2_19
    );
  Mmux_n0002_Result_0_1 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Mcompar_n0007_inst_cy_17,
      ADR2 => Q_n0016(4),
      ADR3 => Q_n0021(0),
      O => Q_n0013_0_FROM
    );
  Mmux_rest_Result_0_1 : X_LUT4
    generic map(
      INIT => X"CDC8"
    )
    port map (
      ADR0 => CHOICE21,
      ADR1 => Q_n0013(4),
      ADR2 => CHOICE13,
      ADR3 => Q_n0013(0),
      O => Q_n0013_0_GROM
    );
  Q_n0013_0_XUSED : X_BUF
    port map (
      I => Q_n0013_0_FROM,
      O => Q_n0013(0)
    );
  Q_n0013_0_YUSED : X_BUF
    port map (
      I => Q_n0013_0_GROM,
      O => rest_0_OBUF
    );
  Mmux_n0002_Result_1_1 : X_LUT4
    generic map(
      INIT => X"F3C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Mcompar_n0007_inst_cy_17,
      ADR2 => Q_n0021(1),
      ADR3 => Q_n0016(5),
      O => Q_n0013_1_FROM
    );
  Mmux_rest_Result_1_1 : X_LUT4
    generic map(
      INIT => X"F1E0"
    )
    port map (
      ADR0 => CHOICE21,
      ADR1 => CHOICE13,
      ADR2 => Q_n0013(5),
      ADR3 => Q_n0013(1),
      O => Q_n0013_1_GROM
    );
  Q_n0013_1_XUSED : X_BUF
    port map (
      I => Q_n0013_1_FROM,
      O => Q_n0013(1)
    );
  Q_n0013_1_YUSED : X_BUF
    port map (
      I => Q_n0013_1_GROM,
      O => rest_1_OBUF
    );
  Mmux_n0002_Result_2_1 : X_LUT4
    generic map(
      INIT => X"AACC"
    )
    port map (
      ADR0 => Q_n0021(2),
      ADR1 => Q_n0016(6),
      ADR2 => VCC,
      ADR3 => Mcompar_n0007_inst_cy_17,
      O => Q_n0013_2_FROM
    );
  Mmux_rest_Result_2_1 : X_LUT4
    generic map(
      INIT => X"F1E0"
    )
    port map (
      ADR0 => CHOICE21,
      ADR1 => CHOICE13,
      ADR2 => Q_n0013(6),
      ADR3 => Q_n0013(2),
      O => Q_n0013_2_GROM
    );
  Q_n0013_2_XUSED : X_BUF
    port map (
      I => Q_n0013_2_FROM,
      O => Q_n0013(2)
    );
  Q_n0013_2_YUSED : X_BUF
    port map (
      I => Q_n0013_2_GROM,
      O => rest_2_OBUF
    );
  Mmux_n0002_Result_3_1 : X_LUT4
    generic map(
      INIT => X"F3C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Mcompar_n0007_inst_cy_17,
      ADR2 => Q_n0021(3),
      ADR3 => Q_n0016(7),
      O => Q_n0013_3_FROM
    );
  Mmux_rest_Result_3_1 : X_LUT4
    generic map(
      INIT => X"CDC8"
    )
    port map (
      ADR0 => CHOICE21,
      ADR1 => Q_n0013(7),
      ADR2 => CHOICE13,
      ADR3 => Q_n0013(3),
      O => Q_n0013_3_GROM
    );
  Q_n0013_3_XUSED : X_BUF
    port map (
      I => Q_n0013_3_FROM,
      O => Q_n0013(3)
    );
  Q_n0013_3_YUSED : X_BUF
    port map (
      I => Q_n0013_3_GROM,
      O => rest_3_OBUF
    );
  Msub_n0012_inst_lut2_191 : X_LUT4
    generic map(
      INIT => X"9C93"
    )
    port map (
      ADR0 => Q_n0019(1),
      ADR1 => b_0_IBUF,
      ADR2 => Mcompar_n0006_inst_cy_12,
      ADR3 => Q_n0015(5),
      O => Msub_n0012_inst_lut2_19_FROM
    );
  Msub_n0011_inst_lut2_201 : X_LUT4
    generic map(
      INIT => X"B847"
    )
    port map (
      ADR0 => a_2_IBUF,
      ADR1 => Mcompar_n0005_inst_cy_6,
      ADR2 => Q_n0014(6),
      ADR3 => b_0_IBUF,
      O => Msub_n0012_inst_lut2_19_GROM
    );
  Msub_n0012_inst_lut2_19_XUSED : X_BUF
    port map (
      I => Msub_n0012_inst_lut2_19_FROM,
      O => Msub_n0012_inst_lut2_19
    );
  Msub_n0012_inst_lut2_19_YUSED : X_BUF
    port map (
      I => Msub_n0012_inst_lut2_19_GROM,
      O => Msub_n0011_inst_lut2_20
    );
  Mmux_n0000_Result_0_1 : X_LUT4
    generic map(
      INIT => X"EE22"
    )
    port map (
      ADR0 => Q_n0014(4),
      ADR1 => Mcompar_n0005_inst_cy_6,
      ADR2 => VCC,
      ADR3 => a_0_IBUF,
      O => Q_n0019_0_FROM
    );
  Mmux_n0001_Result_0_1 : X_LUT4
    generic map(
      INIT => X"EE44"
    )
    port map (
      ADR0 => Mcompar_n0006_inst_cy_12,
      ADR1 => Q_n0015(4),
      ADR2 => VCC,
      ADR3 => Q_n0019(0),
      O => Q_n0019_0_GROM
    );
  Q_n0019_0_XUSED : X_BUF
    port map (
      I => Q_n0019_0_FROM,
      O => Q_n0019(0)
    );
  Q_n0019_0_YUSED : X_BUF
    port map (
      I => Q_n0019_0_GROM,
      O => Q_n0021(0)
    );
  Mmux_n0000_Result_1_1 : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Q_n0014(5),
      ADR2 => a_1_IBUF,
      ADR3 => Mcompar_n0005_inst_cy_6,
      O => Q_n0019_1_FROM
    );
  Mmux_n0001_Result_1_1 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => Q_n0015(5),
      ADR1 => VCC,
      ADR2 => Mcompar_n0006_inst_cy_12,
      ADR3 => Q_n0019(1),
      O => Q_n0019_1_GROM
    );
  Q_n0019_1_XUSED : X_BUF
    port map (
      I => Q_n0019_1_FROM,
      O => Q_n0019(1)
    );
  Q_n0019_1_YUSED : X_BUF
    port map (
      I => Q_n0019_1_GROM,
      O => Q_n0021(1)
    );
  Mcompar_n0008_AGEB24 : X_LUT4
    generic map(
      INIT => X"B2BB"
    )
    port map (
      ADR0 => Q_n0013(1),
      ADR1 => b_1_IBUF,
      ADR2 => Q_n0013(0),
      ADR3 => b_0_IBUF,
      O => CHOICE9_FROM
    );
  Mcompar_n0008_AGEB42 : X_LUT4
    generic map(
      INIT => X"8C00"
    )
    port map (
      ADR0 => Q_n0013(2),
      ADR1 => CHOICE11,
      ADR2 => b_2_IBUF,
      ADR3 => CHOICE9,
      O => CHOICE9_GROM
    );
  CHOICE9_XUSED : X_BUF
    port map (
      I => CHOICE9_FROM,
      O => CHOICE9
    );
  CHOICE9_YUSED : X_BUF
    port map (
      I => CHOICE9_GROM,
      O => CHOICE13
    );
  Q_n00041 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => b_3_IBUF,
      ADR1 => b_0_IBUF,
      ADR2 => b_2_IBUF,
      ADR3 => b_1_IBUF,
      O => err_OBUF_FROM
    );
  Mcompar_n0008_AGEB27 : X_LUT4
    generic map(
      INIT => X"F5DD"
    )
    port map (
      ADR0 => b_3_IBUF,
      ADR1 => Q_n0016(7),
      ADR2 => Q_n0021(3),
      ADR3 => Mcompar_n0007_inst_cy_17,
      O => err_OBUF_GROM
    );
  err_OBUF_XUSED : X_BUF
    port map (
      I => err_OBUF_FROM,
      O => err_OBUF
    );
  err_OBUF_YUSED : X_BUF
    port map (
      I => err_OBUF_GROM,
      O => CHOICE11
    );
  Mmux_n0000_Result_2_1 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => Q_n0014(6),
      ADR1 => VCC,
      ADR2 => Mcompar_n0005_inst_cy_6,
      ADR3 => a_2_IBUF,
      O => Q_n0019_2_FROM
    );
  Mmux_n0001_Result_2_1 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => Q_n0015(6),
      ADR1 => VCC,
      ADR2 => Mcompar_n0006_inst_cy_12,
      ADR3 => Q_n0019(2),
      O => Q_n0019_2_GROM
    );
  Q_n0019_2_XUSED : X_BUF
    port map (
      I => Q_n0019_2_FROM,
      O => Q_n0019(2)
    );
  Q_n0019_2_YUSED : X_BUF
    port map (
      I => Q_n0019_2_GROM,
      O => Q_n0021(2)
    );
  Mmux_n0000_Result_3_1 : X_LUT4
    generic map(
      INIT => X"AACC"
    )
    port map (
      ADR0 => a_3_IBUF,
      ADR1 => Q_n0014(7),
      ADR2 => VCC,
      ADR3 => Mcompar_n0005_inst_cy_6,
      O => Q_n0019_3_FROM
    );
  Mmux_n0001_Result_3_1 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => Q_n0015(7),
      ADR1 => VCC,
      ADR2 => Mcompar_n0006_inst_cy_12,
      ADR3 => Q_n0019(3),
      O => Q_n0019_3_GROM
    );
  Q_n0019_3_XUSED : X_BUF
    port map (
      I => Q_n0019_3_FROM,
      O => Q_n0019(3)
    );
  Q_n0019_3_YUSED : X_BUF
    port map (
      I => Q_n0019_3_GROM,
      O => Q_n0021(3)
    );
  Mcompar_n0008_AGEB74 : X_LUT4
    generic map(
      INIT => X"0A8E"
    )
    port map (
      ADR0 => Q_n0013(3),
      ADR1 => Q_n0013(2),
      ADR2 => b_3_IBUF,
      ADR3 => b_2_IBUF,
      O => CHOICE21_FROM
    );
  Mcompar_n0008_AGEB75 : X_LUT4
    generic map(
      INIT => X"FFF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => CHOICE13,
      ADR3 => CHOICE21,
      O => CHOICE21_GROM
    );
  CHOICE21_XUSED : X_BUF
    port map (
      I => CHOICE21_FROM,
      O => CHOICE21
    );
  CHOICE21_YUSED : X_BUF
    port map (
      I => CHOICE21_GROM,
      O => y_0_OBUF
    );
  Msub_n0009_inst_lut2_181 : X_LUT4
    generic map(
      INIT => X"E21D"
    )
    port map (
      ADR0 => Q_n0016(4),
      ADR1 => Mcompar_n0007_inst_cy_17,
      ADR2 => Q_n0021(0),
      ADR3 => b_0_IBUF,
      O => Msub_n0009_inst_lut2_18_FROM
    );
  Msub_n0009_inst_lut2_201 : X_LUT4
    generic map(
      INIT => X"A959"
    )
    port map (
      ADR0 => b_2_IBUF,
      ADR1 => Q_n0016(6),
      ADR2 => Mcompar_n0007_inst_cy_17,
      ADR3 => Q_n0021(2),
      O => Msub_n0009_inst_lut2_18_GROM
    );
  Msub_n0009_inst_lut2_18_XUSED : X_BUF
    port map (
      I => Msub_n0009_inst_lut2_18_FROM,
      O => Msub_n0009_inst_lut2_18
    );
  Msub_n0009_inst_lut2_18_YUSED : X_BUF
    port map (
      I => Msub_n0009_inst_lut2_18_GROM,
      O => Msub_n0009_inst_lut2_20
    );
  NlwBlock_devider_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;