devider_timesim.vhd

本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.

  Mcompar_n0005_inst_cy_6_COUTUSED : X_BUF
    port map (
      I => Mcompar_n0005_inst_cy_6_CYMUXG,
      O => Mcompar_n0005_inst_cy_6
    );
  Mcompar_n0005_inst_cy_6_35 : X_MUX2
    port map (
      IA => b_3_IBUF,
      IB => Mcompar_n0005_inst_cy_5,
      SEL => Mcompar_n0005_inst_lut2_6,
      O => Mcompar_n0005_inst_cy_6_CYMUXG
    );
  Mcompar_n0005_inst_cy_6_CYINIT_36 : X_BUF
    port map (
      I => Mcompar_n0005_inst_cy_4,
      O => Mcompar_n0005_inst_cy_6_CYINIT
    );
  Mcompar_n0007_inst_cy_15_LOGIC_ZERO_37 : X_ZERO
    port map (
      O => Mcompar_n0007_inst_cy_15_LOGIC_ZERO
    );
  Mcompar_n0007_inst_cy_14_38 : X_MUX2
    port map (
      IA => b_0_IBUF,
      IB => Mcompar_n0007_inst_cy_15_LOGIC_ZERO,
      SEL => Mcompar_n0007_inst_lut2_14,
      O => Mcompar_n0007_inst_cy_14
    );
  Mcompar_n0007_inst_lut2_141 : X_LUT4
    generic map(
      INIT => X"A959"
    )
    port map (
      ADR0 => b_0_IBUF,
      ADR1 => Q_n0015(5),
      ADR2 => Mcompar_n0006_inst_cy_12,
      ADR3 => Q_n0019(1),
      O => Mcompar_n0007_inst_lut2_14
    );
  Mcompar_n0007_inst_lut2_151 : X_LUT4
    generic map(
      INIT => X"99A5"
    )
    port map (
      ADR0 => b_1_IBUF,
      ADR1 => Q_n0019(2),
      ADR2 => Q_n0015(6),
      ADR3 => Mcompar_n0006_inst_cy_12,
      O => Mcompar_n0007_inst_lut2_15
    );
  Mcompar_n0007_inst_cy_15_COUTUSED : X_BUF
    port map (
      I => Mcompar_n0007_inst_cy_15_CYMUXG,
      O => Mcompar_n0007_inst_cy_15
    );
  Mcompar_n0007_inst_cy_15_39 : X_MUX2
    port map (
      IA => b_1_IBUF,
      IB => Mcompar_n0007_inst_cy_14,
      SEL => Mcompar_n0007_inst_lut2_15,
      O => Mcompar_n0007_inst_cy_15_CYMUXG
    );
  Mcompar_n0007_inst_cy_16_40 : X_MUX2
    port map (
      IA => b_2_IBUF,
      IB => Mcompar_n0007_inst_cy_17_CYINIT,
      SEL => Mcompar_n0007_inst_lut2_16,
      O => Mcompar_n0007_inst_cy_16
    );
  Mcompar_n0007_inst_lut2_161 : X_LUT4
    generic map(
      INIT => X"A695"
    )
    port map (
      ADR0 => b_2_IBUF,
      ADR1 => Mcompar_n0006_inst_cy_12,
      ADR2 => Q_n0019(3),
      ADR3 => Q_n0015(7),
      O => Mcompar_n0007_inst_lut2_16
    );
  Mcompar_n0007_inst_lut2_1711 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => b_3_IBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_n0007_inst_lut2_17
    );
  Mcompar_n0007_inst_cy_17_COUTUSED : X_BUF
    port map (
      I => Mcompar_n0007_inst_cy_17_CYMUXG,
      O => Mcompar_n0007_inst_cy_17
    );
  Mcompar_n0007_inst_cy_17_41 : X_MUX2
    port map (
      IA => b_3_IBUF,
      IB => Mcompar_n0007_inst_cy_16,
      SEL => Mcompar_n0007_inst_lut2_17,
      O => Mcompar_n0007_inst_cy_17_CYMUXG
    );
  Mcompar_n0007_inst_cy_17_CYINIT_42 : X_BUF
    port map (
      I => Mcompar_n0007_inst_cy_15,
      O => Mcompar_n0007_inst_cy_17_CYINIT
    );
  Q_n0016_4_LOGIC_ONE_43 : X_ONE
    port map (
      O => Q_n0016_4_LOGIC_ONE
    );
  Msub_n0012_inst_cy_18_44 : X_MUX2
    port map (
      IA => Q_n0021(0),
      IB => Q_n0016_4_CYINIT,
      SEL => Msub_n0012_inst_lut2_18,
      O => Msub_n0012_inst_cy_18
    );
  Msub_n0012_inst_sum_0 : X_XOR2
    port map (
      I0 => Q_n0016_4_CYINIT,
      I1 => Msub_n0012_inst_lut2_18,
      O => Q_n0016_4_XORF
    );
  Msub_n0012_inst_lut2_1811 : X_LUT4
    generic map(
      INIT => X"330F"
    )
    port map (
      ADR0 => Q_n0021(0),
      ADR1 => Q_n0019(0),
      ADR2 => Q_n0015(4),
      ADR3 => Mcompar_n0006_inst_cy_12,
      O => Msub_n0012_inst_lut2_18
    );
  Q_n0016_4_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => Q_n0021(1),
      ADR1 => VCC,
      ADR2 => Msub_n0012_inst_lut2_19,
      ADR3 => VCC,
      O => Q_n0016_4_GROM
    );
  Q_n0016_4_COUTUSED : X_BUF
    port map (
      I => Q_n0016_4_CYMUXG,
      O => Msub_n0012_inst_cy_19
    );
  Q_n0016_4_XUSED : X_BUF
    port map (
      I => Q_n0016_4_XORF,
      O => Q_n0016(4)
    );
  Q_n0016_4_YUSED : X_BUF
    port map (
      I => Q_n0016_4_XORG,
      O => Q_n0016(5)
    );
  Msub_n0012_inst_cy_19_45 : X_MUX2
    port map (
      IA => Q_n0021(1),
      IB => Msub_n0012_inst_cy_18,
      SEL => Q_n0016_4_GROM,
      O => Q_n0016_4_CYMUXG
    );
  Msub_n0012_inst_sum_1 : X_XOR2
    port map (
      I0 => Msub_n0012_inst_cy_18,
      I1 => Q_n0016_4_GROM,
      O => Q_n0016_4_XORG
    );
  Q_n0016_4_CYINIT_46 : X_BUF
    port map (
      I => Q_n0016_4_LOGIC_ONE,
      O => Q_n0016_4_CYINIT
    );
  Msub_n0012_inst_cy_20_47 : X_MUX2
    port map (
      IA => Q_n0021(2),
      IB => Q_n0016_6_CYINIT,
      SEL => Q_n0016_6_FROM,
      O => Msub_n0012_inst_cy_20
    );
  Msub_n0012_inst_sum_2 : X_XOR2
    port map (
      I0 => Q_n0016_6_CYINIT,
      I1 => Q_n0016_6_FROM,
      O => Q_n0016_6_XORF
    );
  Q_n0016_6_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => Q_n0021(2),
      ADR1 => Msub_n0012_inst_lut2_20,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Q_n0016_6_FROM
    );
  Msub_n0012_inst_lut2_211 : X_LUT4
    generic map(
      INIT => X"E41B"
    )
    port map (
      ADR0 => Mcompar_n0006_inst_cy_12,
      ADR1 => Q_n0015(7),
      ADR2 => Q_n0019(3),
      ADR3 => b_2_IBUF,
      O => Msub_n0012_inst_lut2_21
    );
  Q_n0016_6_XUSED : X_BUF
    port map (
      I => Q_n0016_6_XORF,
      O => Q_n0016(6)
    );
  Q_n0016_6_YUSED : X_BUF
    port map (
      I => Q_n0016_6_XORG,
      O => Q_n0016(7)
    );
  Msub_n0012_inst_sum_3 : X_XOR2
    port map (
      I0 => Msub_n0012_inst_cy_20,
      I1 => Msub_n0012_inst_lut2_21,
      O => Q_n0016_6_XORG
    );
  Q_n0016_6_CYINIT_48 : X_BUF
    port map (
      I => Msub_n0012_inst_cy_19,
      O => Q_n0016_6_CYINIT
    );
  Mcompar_n0006_inst_cy_10_LOGIC_ZERO_49 : X_ZERO
    port map (
      O => Mcompar_n0006_inst_cy_10_LOGIC_ZERO
    );
  Mcompar_n0006_inst_cy_9_50 : X_MUX2
    port map (
      IA => b_0_IBUF,
      IB => Mcompar_n0006_inst_cy_10_LOGIC_ZERO,
      SEL => Mcompar_n0006_inst_lut2_9,
      O => Mcompar_n0006_inst_cy_9
    );
  Mcompar_n0006_inst_lut2_91 : X_LUT4
    generic map(
      INIT => X"A695"
    )
    port map (
      ADR0 => b_0_IBUF,
      ADR1 => Mcompar_n0005_inst_cy_6,
      ADR2 => a_2_IBUF,
      ADR3 => Q_n0014(6),
      O => Mcompar_n0006_inst_lut2_9
    );
  Mcompar_n0006_inst_lut2_101 : X_LUT4
    generic map(
      INIT => X"A599"
    )
    port map (
      ADR0 => b_1_IBUF,
      ADR1 => Q_n0014(7),
      ADR2 => a_3_IBUF,
      ADR3 => Mcompar_n0005_inst_cy_6,
      O => Mcompar_n0006_inst_lut2_10
    );
  Mcompar_n0006_inst_cy_10_COUTUSED : X_BUF
    port map (
      I => Mcompar_n0006_inst_cy_10_CYMUXG,
      O => Mcompar_n0006_inst_cy_10
    );
  Mcompar_n0006_inst_cy_10_51 : X_MUX2
    port map (
      IA => b_1_IBUF,
      IB => Mcompar_n0006_inst_cy_9,
      SEL => Mcompar_n0006_inst_lut2_10,
      O => Mcompar_n0006_inst_cy_10_CYMUXG
    );
  Mcompar_n0006_inst_cy_11_52 : X_MUX2
    port map (
      IA => b_2_IBUF,
      IB => Mcompar_n0006_inst_cy_12_CYINIT,
      SEL => Mcompar_n0006_inst_lut2_11,
      O => Mcompar_n0006_inst_cy_11
    );
  Mcompar_n0006_inst_lut2_1111 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => b_2_IBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_n0006_inst_lut2_11
    );
  Mcompar_n0006_inst_lut2_1211 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => b_3_IBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_n0006_inst_lut2_12
    );
  Mcompar_n0006_inst_cy_12_COUTUSED : X_BUF
    port map (
      I => Mcompar_n0006_inst_cy_12_CYMUXG,
      O => Mcompar_n0006_inst_cy_12
    );
  Mcompar_n0006_inst_cy_12_53 : X_MUX2
    port map (
      IA => b_3_IBUF,
      IB => Mcompar_n0006_inst_cy_11,
      SEL => Mcompar_n0006_inst_lut2_12,
      O => Mcompar_n0006_inst_cy_12_CYMUXG
    );
  Mcompar_n0006_inst_cy_12_CYINIT_54 : X_BUF
    port map (
      I => Mcompar_n0006_inst_cy_10,
      O => Mcompar_n0006_inst_cy_12_CYINIT
    );
  Q_n0013_4_LOGIC_ONE_55 : X_ONE
    port map (
      O => Q_n0013_4_LOGIC_ONE
    );
  Msub_n0009_inst_cy_18_56 : X_MUX2
    port map (
      IA => Q_n0013(0),
      IB => Q_n0013_4_CYINIT,
      SEL => Q_n0013_4_FROM,
      O => Msub_n0009_inst_cy_18
    );
  Msub_n0009_inst_sum_0 : X_XOR2
    port map (
      I0 => Q_n0013_4_CYINIT,
      I1 => Q_n0013_4_FROM,
      O => Q_n0013_4_XORF
    );
  Q_n0013_4_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => Q_n0013(0),
      ADR1 => Msub_n0009_inst_lut2_18,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Q_n0013_4_FROM
    );
  Q_n0013_4_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => Q_n0013(1),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Msub_n0009_inst_lut2_19,
      O => Q_n0013_4_GROM
    );
  Q_n0013_4_COUTUSED : X_BUF
    port map (
      I => Q_n0013_4_CYMUXG,
      O => Msub_n0009_inst_cy_19
    );
  Q_n0013_4_XUSED : X_BUF
    port map (
      I => Q_n0013_4_XORF,
      O => Q_n0013(4)
    );
  Q_n0013_4_YUSED : X_BUF
    port map (
      I => Q_n0013_4_XORG,
      O => Q_n0013(5)
    );
  Msub_n0009_inst_cy_19_57 : X_MUX2
    port map (
      IA => Q_n0013(1),
      IB => Msub_n0009_inst_cy_18,
      SEL => Q_n0013_4_GROM,
      O => Q_n0013_4_CYMUXG
    );
  Msub_n0009_inst_sum_1 : X_XOR2
    port map (
      I0 => Msub_n0009_inst_cy_18,
      I1 => Q_n0013_4_GROM,
      O => Q_n0013_4_XORG
    );
  Q_n0013_4_CYINIT_58 : X_BUF
    port map (
      I => Q_n0013_4_LOGIC_ONE,
      O => Q_n0013_4_CYINIT
    );
  Msub_n0009_inst_cy_20_59 : X_MUX2
    port map (
      IA => Q_n0013(2),
      IB => Q_n0013_6_CYINIT,
      SEL => Q_n0013_6_FROM,
      O => Msub_n0009_inst_cy_20
    );
  Msub_n0009_inst_sum_2 : X_XOR2
    port map (
      I0 => Q_n0013_6_CYINIT,
      I1 => Q_n0013_6_FROM,
      O => Q_n0013_6_XORF
    );
  Q_n0013_6_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => Q_n0013(2),
      ADR1 => Msub_n0009_inst_lut2_20,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Q_n0013_6_FROM
    );
  Msub_n0009_inst_lut2_211 : X_LUT4
    generic map(
      INIT => X"C963"
    )
    port map (
      ADR0 => Mcompar_n0007_inst_cy_17,
      ADR1 => b_3_IBUF,
      ADR2 => Q_n0016(7),
      ADR3 => Q_n0021(3),
      O => Msub_n0009_inst_lut2_21
    );
  Q_n0013_6_XUSED : X_BUF
    port map (
      I => Q_n0013_6_XORF,
      O => Q_n0013(6)
    );
  Q_n0013_6_YUSED : X_BUF
    port map (
      I => Q_n0013_6_XORG,
      O => Q_n0013(7)
    );
  Msub_n0009_inst_sum_3 : X_XOR2
    port map (
      I0 => Msub_n0009_inst_cy_20,
      I1 => Msub_n0009_inst_lut2_21,
      O => Q_n0013_6_XORG
    );
  Q_n0013_6_CYINIT_60 : X_BUF
    port map (
      I => Msub_n0009_inst_cy_19,
      O => Q_n0013_6_CYINIT
    );
  Q_n0014_4_LOGIC_ONE_61 : X_ONE
    port map (
      O => Q_n0014_4_LOGIC_ONE
    );
  Msub_n0010_inst_cy_18_62 : X_MUX2
    port map (
      IA => a_0_IBUF,
      IB => Q_n0014_4_CYINIT,
      SEL => Msub_n0010_inst_lut2_18,
      O => Msub_n0010_inst_cy_18
    );
  Msub_n0010_inst_sum_0 : X_XOR2
    port map (
      I0 => Q_n0014_4_CYINIT,
      I1 => Msub_n0010_inst_lut2_18,
      O => Q_n0014_4_XORF
    );
  Msub_n0010_inst_lut2_1811 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => a_0_IBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Msub_n0010_inst_lut2_18
    );
  Msub_n0010_inst_lut2_1911 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => a_1_IBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Msub_n0010_inst_lut2_19
    );
  Q_n0014_4_COUTUSED : X_BUF
    port map (
      I => Q_n0014_4_CYMUXG,
      O => Msub_n0010_inst_cy_19
    );
  Q_n0014_4_XUSED : X_BUF
    port map (
      I => Q_n0014_4_XORF,
      O => Q_n0014(4)
    );
  Q_n0014_4_YUSED : X_BUF
    port map (
      I => Q_n0014_4_XORG,
      O => Q_n0014(5)
    );
  Msub_n0010_inst_cy_19_63 : X_MUX2
    port map (
      IA => a_1_IBUF,
      IB => Msub_n0010_inst_cy_18,
      SEL => Msub_n0010_inst_lut2_19,
      O => Q_n0014_4_CYMUXG
    );
  Msub_n0010_inst_sum_1 : X_XOR2
    port map (
      I0 => Msub_n0010_inst_cy_18,
      I1 => Msub_n0010_inst_lut2_19,
      O => Q_n0014_4_XORG
    );
  Q_n0014_4_CYINIT_64 : X_BUF
    port map (
      I => Q_n0014_4_LOGIC_ONE,
      O => Q_n0014_4_CYINIT
    );
  Msub_n0010_inst_cy_20_65 : X_MUX2
    port map (
      IA => a_2_IBUF,
      IB => Q_n0014_6_CYINIT,
      SEL => Msub_n0010_inst_lut2_20,
      O => Msub_n0010_inst_cy_20
    );
  Msub_n0010_inst_sum_2 : X_XOR2
    port map (
      I0 => Q_n0014_6_CYINIT,
      I1 => Msub_n0010_inst_lut2_20,
      O => Q_n0014_6_XORF
    );
  Msub_n0010_inst_lut2_2011 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => a_2_IBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Msub_n0010_inst_lut2_20
    );
  Msub_n0010_inst_lut2_211 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => a_3_IBUF,
      ADR1 => VCC,
      ADR2 => b_0_IBUF,
      ADR3 => VCC,
      O => Msub_n0010_inst_lut2_21
    );
  Q_n0014_6_XUSED : X_BUF
    port map (
      I => Q_n0014_6_XORF,
      O => Q_n0014(6)
    );
  Q_n0014_6_YUSED : X_BUF
    port map (
      I => Q_n0014_6_XORG,
      O => Q_n0014(7)
    );
  Msub_n0010_inst_sum_3 : X_XOR2
    port map (
      I0 => Msub_n0010_inst_cy_20,
      I1 => Msub_n0010_inst_lut2_21,
      O => Q_n0014_6_XORG
    );
  Q_n0014_6_CYINIT_66 : X_BUF
    port map (
      I => Msub_n0010_inst_cy_19,
      O => Q_n0014_6_CYINIT
    );
  Q_n0015_4_LOGIC_ONE_67 : X_ONE
    port map (
      O => Q_n0015_4_LOGIC_ONE