sram.v

sram 读写小程序

module  sram (clk_fpga,    //fpga时钟
              clk_sram,    //sram时钟
              sramadd,     //sram地址
              data_sram,   //sram数据
              data_fpga,   //fpga输出数据
              we_sram,     //sram写使能信号
              iosel0,      //见NetDisplay板内协议
              iowe,        //单片机与FPGA使能信号
              h_sel,       //行选择信号
              oe,          //oe极性
              sclk,        //移位时钟
              rclk);       //锁存时钟

input  clk_fpga;
input  iosel0;
input  iowe;
input  [7:0]data_sram;
output [15:0]sramadd;
output [7:0]data_fpga;
output we_sram;
output clk_sram;
output sclk;
output rclk;
output oe;
output [3:0]h_sel;

wire  we_sram;
reg  [15:0]sramadd;
reg  [7:0]datasram;
reg  [7:0]data_fpga;
reg  [6:0]count1;     //列计数
reg  [3:0]count2;     //换行信号
reg  [3:0]count3;     //对clk_fpga分频
reg  oe;
reg  rclk;
wire sclk;
wire [3:0]h_sel;
wire clk_sram;
wire reset;

assign  h_sel=count2;
assign  reset=iosel0 && iowe;
assign 	clk_sram=sclk;
assign  we_sram=1'b0;
assign  sclk=count3[3];

/*==========================
  FPGA 对屏的控制
===========================*/
always @ (posedge clk_fpga)

   count3<=count3+1'b1;      //时钟分频

always @ (posedge sclk)

  begin
  if(count1==7'h4F)           //列计数
     count1<=7'h00;
   else
     count1<=count1+1'b1;
  end

always @ (posedge clk_fpga)
 begin
 	if (count1==7'h00 && count3==4'hA)    //锁存时钟
 	  rclk<=1'b1;
 	else
 	  rclk<=1'b0;
 end

always @ (posedge rclk)

 count2<=count2+1'b1;              //锁存同时换行

always @(posedge sclk)
 begin

   if((count1>=7'h4C) || (count1<=7'h03))    //消隐
     oe<=1'b1;
   else
     oe<=1'b0;
 end

/*============================
   FPGA对sram的控制
=============================*/
always @ (posedge clk_sram)
   
   data_fpga<=data_sram;         //数据输出
   
always @ (posedge clk_sram)
  begin
  	if (reset)                   //sram  address control
  	 sramadd<=16'h1000;
  	else if(count1==7'h4F)       //count1==7'h50)  //&& sramadd==16'h1051)
  	 sramadd<=16'h1000;
  	else
  	 sramadd<=sramadd+1'b1;
  end
endmodule