📄 fen20.rpt
字号:
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\rcd2005\eda\homework\24miao\fen20.rpt
fen20
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 11 AND2 0 2 0 3 |LPM_ADD_SUB:73|addcore:adder|:63
- 8 - A 11 DFFE + 0 3 0 1 counter4 (:3)
- 7 - A 11 DFFE + 0 3 0 2 counter3 (:4)
- 6 - A 11 DFFE + 0 3 0 3 counter2 (:5)
- 5 - A 11 DFFE + 0 2 0 2 counter1 (:6)
- 1 - A 11 DFFE + 0 0 0 3 counter0 (:7)
- 3 - A 11 DFFE + 0 1 1 0 clk1 (:8)
- 4 - A 11 OR2 ! 0 4 0 4 :30
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\rcd2005\eda\homework\24miao\fen20.rpt
fen20
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\rcd2005\eda\homework\24miao\fen20.rpt
fen20
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 6 clk
Device-Specific Information: d:\rcd2005\eda\homework\24miao\fen20.rpt
fen20
** EQUATIONS **
clk : INPUT;
-- Node name is ':8' = 'clk1'
-- Equation name is 'clk1', location is LC3_A11, type is buried.
clk1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = clk1 & !_LC4_A11
# !clk1 & _LC4_A11;
-- Node name is 'clk5hz'
-- Equation name is 'clk5hz', type is output
clk5hz = clk1;
-- Node name is ':7' = 'counter0'
-- Equation name is 'counter0', location is LC1_A11, type is buried.
counter0 = DFFE(!counter0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':6' = 'counter1'
-- Equation name is 'counter1', location is LC5_A11, type is buried.
counter1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !counter0 & counter1 & !_LC4_A11
# counter0 & !counter1 & !_LC4_A11;
-- Node name is ':5' = 'counter2'
-- Equation name is 'counter2', location is LC6_A11, type is buried.
counter2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !counter1 & counter2 & !_LC4_A11
# !counter0 & counter2 & !_LC4_A11
# counter0 & counter1 & !counter2 & !_LC4_A11;
-- Node name is ':4' = 'counter3'
-- Equation name is 'counter3', location is LC7_A11, type is buried.
counter3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !counter2 & counter3 & !_LC4_A11
# counter3 & !_LC2_A11 & !_LC4_A11
# counter2 & !counter3 & _LC2_A11 & !_LC4_A11;
-- Node name is ':3' = 'counter4'
-- Equation name is 'counter4', location is LC8_A11, type is buried.
counter4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = counter4 & !_LC2_A11
# counter2 & counter3 & !counter4 & _LC2_A11
# counter2 & !counter3 & counter4
# !counter2 & counter3 & counter4;
-- Node name is '|LPM_ADD_SUB:73|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A11', type is buried
_LC2_A11 = LCELL( _EQ006);
_EQ006 = counter0 & counter1;
-- Node name is ':30'
-- Equation name is '_LC4_A11', type is buried
!_LC4_A11 = _LC4_A11~NOT;
_LC4_A11~NOT = LCELL( _EQ007);
_EQ007 = counter2
# counter3
# !counter4
# !_LC2_A11;
Project Information d:\rcd2005\eda\homework\24miao\fen20.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 26,346K
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