fen75.vhd

来自「24秒倒计时系统（有跑马灯） 利用CPLD」· VHDL 代码 · 共 33 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY fen75 IS
PORT(
	CLOCK:IN STD_LOGIC;
	CLK:OUT STD_LOGIC
	);
END fen75;

ARCHITECTURE fen_arc OF fen75 IS
SIGNAL COUNTER:INTEGER RANGE 0 TO 74;
SIGNAL TEMP1,TEMP2:STD_LOGIC;
BEGIN
PROCESS(CLOCK)
BEGIN
IF RISING_EDGE(CLOCK) THEN
	IF COUNTER=74 THEN
		COUNTER<=0;
		TEMP1<=NOT TEMP1;
	ELSE
		COUNTER<=COUNTER+1;
	END IF;
END IF;
IF FALLING_EDGE(CLOCK) THEN
	IF COUNTER=37 THEN
		TEMP2<=NOT TEMP2;
	END IF;
END IF;
END PROCESS;
CLK<=TEMP1 XOR TEMP2;
END fen_arc;