📄 ledrun.rpt
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-- Node name is ':30' = 'f9'
-- Equation name is 'f9', location is LC4_A10, type is buried.
f9 = DFFE( _EQ031, f_scan1, VCC, VCC, VCC);
_EQ031 = f9 & !mode
# !f17 & mode
# !f0 & mode;
-- Node name is ':29' = 'f10'
-- Equation name is 'f10', location is LC1_A10, type is buried.
f10 = DFFE( _EQ032, f_scan1, VCC, VCC, VCC);
_EQ032 = f9 & mode
# f10 & !mode;
-- Node name is ':28' = 'f11'
-- Equation name is 'f11', location is LC2_A10, type is buried.
f11 = DFFE( _EQ033, f_scan1, VCC, VCC, VCC);
_EQ033 = f10 & mode
# f11 & !mode;
-- Node name is ':27' = 'f12'
-- Equation name is 'f12', location is LC8_A10, type is buried.
f12 = DFFE( _EQ034, f_scan1, VCC, VCC, VCC);
_EQ034 = f11 & mode
# f12 & !mode;
-- Node name is ':26' = 'f13'
-- Equation name is 'f13', location is LC8_A17, type is buried.
f13 = DFFE( _EQ035, f_scan1, VCC, VCC, VCC);
_EQ035 = f12 & mode
# f13 & !mode;
-- Node name is ':25' = 'f14'
-- Equation name is 'f14', location is LC7_A17, type is buried.
f14 = DFFE( _EQ036, f_scan1, VCC, VCC, VCC);
_EQ036 = f13 & mode
# f14 & !mode;
-- Node name is ':24' = 'f15'
-- Equation name is 'f15', location is LC3_A17, type is buried.
f15 = DFFE( _EQ037, f_scan1, VCC, VCC, VCC);
_EQ037 = f14 & mode
# f15 & !mode;
-- Node name is ':23' = 'f16'
-- Equation name is 'f16', location is LC5_A10, type is buried.
f16 = DFFE( _EQ038, f_scan1, VCC, VCC, VCC);
_EQ038 = f15 & mode
# f16 & !mode;
-- Node name is ':22' = 'f17'
-- Equation name is 'f17', location is LC7_A10, type is buried.
f17 = DFFE( _EQ039, f_scan1, VCC, VCC, VCC);
_EQ039 = f16 & mode
# f17 & !mode;
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = f0;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = f1;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = f2;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = f3;
-- Node name is 'q4'
-- Equation name is 'q4', type is output
q4 = f4;
-- Node name is 'q5'
-- Equation name is 'q5', type is output
q5 = f5;
-- Node name is 'q6'
-- Equation name is 'q6', type is output
q6 = f6;
-- Node name is 'q7'
-- Equation name is 'q7', type is output
q7 = f7;
-- Node name is 'q8'
-- Equation name is 'q8', type is output
q8 = f8;
-- Node name is 'q9'
-- Equation name is 'q9', type is output
q9 = f9;
-- Node name is 'q10'
-- Equation name is 'q10', type is output
q10 = f10;
-- Node name is 'q11'
-- Equation name is 'q11', type is output
q11 = f11;
-- Node name is 'q12'
-- Equation name is 'q12', type is output
q12 = f12;
-- Node name is 'q13'
-- Equation name is 'q13', type is output
q13 = f13;
-- Node name is 'q14'
-- Equation name is 'q14', type is output
q14 = f14;
-- Node name is 'q15'
-- Equation name is 'q15', type is output
q15 = f15;
-- Node name is 'q16'
-- Equation name is 'q16', type is output
q16 = f16;
-- Node name is 'q17'
-- Equation name is 'q17', type is output
q17 = f17;
-- Node name is '|LPM_ADD_SUB:316|addcore:adder|:127' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A20', type is buried
_LC6_A20 = LCELL( _EQ040);
_EQ040 = d_ff0~101 & d_ff1~101;
-- Node name is '|LPM_ADD_SUB:316|addcore:adder|:135' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A20', type is buried
_LC4_A20 = LCELL( _EQ041);
_EQ041 = d_ff0~101 & d_ff1~101 & d_ff2~101 & d_ff3~101;
-- Node name is '|LPM_ADD_SUB:316|addcore:adder|:139' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A14', type is buried
_LC2_A14 = LCELL( _EQ042);
_EQ042 = d_ff4~101 & _LC4_A20;
-- Node name is '|LPM_ADD_SUB:316|addcore:adder|:147' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A14', type is buried
_LC5_A14 = LCELL( _EQ043);
_EQ043 = d_ff4~101 & d_ff5~101 & d_ff6~101 & _LC4_A20;
-- Node name is '|LPM_ADD_SUB:316|addcore:adder|:155' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A14', type is buried
_LC4_A14 = LCELL( _EQ044);
_EQ044 = d_ff7~101 & d_ff8~101 & _LC5_A14;
-- Node name is '|LPM_ADD_SUB:316|addcore:adder|:163' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A18', type is buried
_LC7_A18 = LCELL( _EQ045);
_EQ045 = d_ff9~101 & d_ff10~101 & _LC4_A14;
-- Node name is '|LPM_ADD_SUB:316|addcore:adder|:167' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A18', type is buried
_LC2_A18 = LCELL( _EQ046);
_EQ046 = d_ff9~101 & d_ff10~101 & d_ff11~101 & _LC4_A14;
-- Node name is '|LPM_ADD_SUB:316|addcore:adder|:171' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A13', type is buried
_LC4_A13 = LCELL( _EQ047);
_EQ047 = d_ff12~101 & _LC2_A18;
-- Node name is '|LPM_ADD_SUB:316|addcore:adder|:179' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A13', type is buried
_LC2_A13 = LCELL( _EQ048);
_EQ048 = d_ff12~101 & d_ff13~101 & d_ff14~101 & _LC2_A18;
-- Node name is '|LPM_ADD_SUB:316|addcore:adder|:187' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A21', type is buried
_LC3_A21 = LCELL( _EQ049);
_EQ049 = d_ff15~101 & d_ff16~101 & _LC2_A13;
-- Node name is '|LPM_ADD_SUB:316|addcore:adder|:195' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A21', type is buried
_LC7_A21 = LCELL( _EQ050);
_EQ050 = d_ff17~101 & d_ff18~101 & _LC3_A21;
-- Node name is '~107~1'
-- Equation name is '~107~1', location is LC2_A21, type is buried.
-- synthesized logic cell
_LC2_A21 = LCELL( _EQ051);
_EQ051 = !d_ff17~101
# !d_ff19~101
# !d_ff18~101;
-- Node name is ':107'
-- Equation name is '_LC4_A21', type is buried
_LC4_A21 = LCELL( _EQ052);
_EQ052 = !d_ff20~101
# !d_ff16~101 & _LC1_A18
# _LC2_A21;
-- Node name is ':132'
-- Equation name is '_LC1_A18', type is buried
_LC1_A18 = LCELL( _EQ053);
_EQ053 = !d_ff15~101
# !d_ff10~101 & _LC8_A13
# _LC8_A13 & _LC8_A14;
-- Node name is '~134~1'
-- Equation name is '~134~1', location is LC8_A13, type is buried.
-- synthesized logic cell
_LC8_A13 = LCELL( _EQ054);
_EQ054 = !d_ff11~101 & !d_ff12~101 & !d_ff13~101 & !d_ff14~101;
-- Node name is ':159'
-- Equation name is '_LC8_A14', type is buried
_LC8_A14 = LCELL( _EQ055);
_EQ055 = !d_ff7~101 & !d_ff8~101 & !d_ff9~101;
Project Information h:\24miao\ledrun.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 20,768K
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