📄 xset.vhd
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library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity xset is
port(time:in std_logic_vector(5 downto 0);
reset:in std_logic;
clk:in std_logic;
sel:out std_logic;
d_out:out std_logic_vector(3 downto 0)
);
end xset;
architecture arc_xset of xset is
signal sel1:std_logic;
begin
process(clk,reset,time)
begin
if reset='0' then
sel<='0';
d_out<="0000";
sel1<='0';
else
if (clk='1' and clk'event) then
sel1<=not sel1;
end if;
sel<=sel1;
case sel1 is
when '0'=>d_out(3)<='0';
d_out(2)<='0';
d_out(1)<=time(5);
d_out(0)<=time(4);
when '1'=>d_out<=time(3 downto 0);
when others=>null;
end case;
end if;
end process;
end arc_xset;
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