📄 24second.rpt
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Device-Specific Information: h:\24miao\24second.rpt
24second
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - C 29 AND2 0 2 0 3 |FEN75:8|LPM_ADD_SUB:98|addcore:adder|:121
- 3 - C 29 AND2 0 3 0 3 |FEN75:8|LPM_ADD_SUB:98|addcore:adder|:129
- 3 - C 33 AND2 0 2 0 1 |FEN75:8|LPM_ADD_SUB:98|addcore:adder|:133
- 4 - C 33 DFFE + 0 3 0 2 |FEN75:8|COUNTER6 (|FEN75:8|:3)
- 5 - C 33 DFFE + 0 3 0 3 |FEN75:8|COUNTER5 (|FEN75:8|:4)
- 6 - C 33 DFFE + 0 2 0 4 |FEN75:8|COUNTER4 (|FEN75:8|:5)
- 1 - C 29 DFFE + 0 3 0 3 |FEN75:8|COUNTER3 (|FEN75:8|:6)
- 6 - C 29 DFFE + 0 2 0 4 |FEN75:8|COUNTER2 (|FEN75:8|:7)
- 7 - C 29 DFFE + 0 2 0 3 |FEN75:8|COUNTER1 (|FEN75:8|:8)
- 8 - C 29 DFFE + 0 1 0 4 |FEN75:8|COUNTER0 (|FEN75:8|:9)
- 3 - C 06 DFFE + 0 1 0 1 |FEN75:8|TEMP1 (|FEN75:8|:10)
- 1 - C 33 DFFE + 0 3 0 1 |FEN75:8|TEMP2 (|FEN75:8|:11)
- 2 - C 33 OR2 s 0 4 0 1 |FEN75:8|~41~1
- 5 - C 29 OR2 ! 0 4 0 8 |FEN75:8|:41
- 7 - C 33 AND2 s 0 3 0 1 |FEN75:8|~251~1
- 2 - C 29 AND2 s 0 3 0 1 |FEN75:8|~251~2
- 1 - C 06 OR2 0 2 0 7 |FEN75:8|:306
- 1 - C 07 AND2 0 2 0 1 |FEN100:9|LPM_ADD_SUB:85|addcore:adder|:67
- 5 - C 14 AND2 0 4 0 2 |FEN100:9|LPM_ADD_SUB:85|addcore:adder|:75
- 6 - C 14 DFFE 0 4 0 1 |FEN100:9|counter5 (|FEN100:9|:3)
- 7 - C 14 DFFE 0 3 0 2 |FEN100:9|counter4 (|FEN100:9|:4)
- 4 - C 14 DFFE 0 4 0 2 |FEN100:9|counter3 (|FEN100:9|:5)
- 8 - C 14 DFFE 0 4 0 3 |FEN100:9|counter2 (|FEN100:9|:6)
- 2 - C 14 DFFE 0 3 0 4 |FEN100:9|counter1 (|FEN100:9|:7)
- 2 - C 07 DFFE 0 1 0 5 |FEN100:9|counter0 (|FEN100:9|:8)
- 2 - C 06 DFFE 0 2 0 19 |FEN100:9|clk1 (|FEN100:9|:9)
- 3 - C 14 OR2 s 0 3 0 1 |FEN100:9|~35~1
- 1 - C 14 OR2 ! 0 4 0 6 |FEN100:9|:35
- 1 - E 15 AND2 0 2 0 1 |FEN100:10|LPM_ADD_SUB:85|addcore:adder|:67
- 5 - E 18 AND2 0 4 0 2 |FEN100:10|LPM_ADD_SUB:85|addcore:adder|:75
- 6 - E 18 DFFE 0 4 0 1 |FEN100:10|counter5 (|FEN100:10|:3)
- 7 - E 18 DFFE 0 3 0 2 |FEN100:10|counter4 (|FEN100:10|:4)
- 4 - E 18 DFFE 0 4 0 2 |FEN100:10|counter3 (|FEN100:10|:5)
- 8 - E 18 DFFE 0 4 0 3 |FEN100:10|counter2 (|FEN100:10|:6)
- 1 - E 18 DFFE 0 3 0 4 |FEN100:10|counter1 (|FEN100:10|:7)
- 2 - E 15 DFFE 0 1 0 5 |FEN100:10|counter0 (|FEN100:10|:8)
- 7 - E 15 DFFE 0 2 0 1 |FEN100:10|clk1 (|FEN100:10|:9)
- 3 - E 18 OR2 s 0 3 0 1 |FEN100:10|~35~1
- 2 - E 18 OR2 ! 0 4 0 6 |FEN100:10|:35
- 7 - C 35 AND2 0 2 0 1 |LEDRUN:40|LPM_ADD_SUB:316|addcore:adder|:127
- 2 - C 35 AND2 0 4 0 4 |LEDRUN:40|LPM_ADD_SUB:316|addcore:adder|:135
- 4 - C 30 AND2 0 2 0 1 |LEDRUN:40|LPM_ADD_SUB:316|addcore:adder|:139
- 2 - C 30 AND2 0 4 0 3 |LEDRUN:40|LPM_ADD_SUB:316|addcore:adder|:147
- 7 - C 25 AND2 0 3 0 4 |LEDRUN:40|LPM_ADD_SUB:316|addcore:adder|:155
- 5 - C 25 AND2 0 3 0 1 |LEDRUN:40|LPM_ADD_SUB:316|addcore:adder|:163
- 2 - C 25 AND2 0 4 0 4 |LEDRUN:40|LPM_ADD_SUB:316|addcore:adder|:167
- 6 - C 20 AND2 0 2 0 1 |LEDRUN:40|LPM_ADD_SUB:316|addcore:adder|:171
- 5 - C 20 AND2 0 4 0 3 |LEDRUN:40|LPM_ADD_SUB:316|addcore:adder|:179
- 3 - C 21 AND2 0 3 0 3 |LEDRUN:40|LPM_ADD_SUB:316|addcore:adder|:187
- 7 - C 21 AND2 0 3 0 2 |LEDRUN:40|LPM_ADD_SUB:316|addcore:adder|:195
- 5 - B 03 DFFE 1 1 0 18 |LEDRUN:40|f_scan1 (|LEDRUN:40|:21)
- 7 - E 06 DFFE 0 5 1 3 |LEDRUN:40|f17 (|LEDRUN:40|:22)
- 8 - B 03 DFFE 0 4 1 3 |LEDRUN:40|f16 (|LEDRUN:40|:23)
- 6 - B 03 DFFE 0 4 1 3 |LEDRUN:40|f15 (|LEDRUN:40|:24)
- 3 - B 14 DFFE 0 4 1 3 |LEDRUN:40|f14 (|LEDRUN:40|:25)
- 2 - B 14 DFFE 0 4 1 3 |LEDRUN:40|f13 (|LEDRUN:40|:26)
- 7 - B 14 DFFE 0 4 1 3 |LEDRUN:40|f12 (|LEDRUN:40|:27)
- 7 - B 12 DFFE 0 4 1 3 |LEDRUN:40|f11 (|LEDRUN:40|:28)
- 6 - B 12 DFFE 0 4 1 3 |LEDRUN:40|f10 (|LEDRUN:40|:29)
- 3 - B 03 DFFE 0 4 1 3 |LEDRUN:40|f9 (|LEDRUN:40|:30)
- 1 - B 03 DFFE 0 4 1 3 |LEDRUN:40|f8 (|LEDRUN:40|:31)
- 8 - B 12 DFFE 0 4 1 3 |LEDRUN:40|f7 (|LEDRUN:40|:32)
- 5 - B 12 DFFE 0 4 1 3 |LEDRUN:40|f6 (|LEDRUN:40|:33)
- 5 - B 14 DFFE 0 4 1 3 |LEDRUN:40|f5 (|LEDRUN:40|:34)
- 1 - B 14 DFFE 0 4 1 3 |LEDRUN:40|f4 (|LEDRUN:40|:35)
- 1 - B 12 DFFE 0 4 1 3 |LEDRUN:40|f3 (|LEDRUN:40|:36)
- 2 - B 12 DFFE 0 4 1 3 |LEDRUN:40|f2 (|LEDRUN:40|:37)
- 3 - B 12 DFFE 0 4 1 3 |LEDRUN:40|f1 (|LEDRUN:40|:38)
- 4 - B 03 DFFE 0 5 1 2 |LEDRUN:40|f0 (|LEDRUN:40|:39)
- 4 - C 21 DFFE 1 3 0 2 |LEDRUN:40|d_ff20~102 (|LEDRUN:40|:63)
- 8 - C 21 DFFE 1 2 0 2 |LEDRUN:40|d_ff19~102 (|LEDRUN:40|:64)
- 5 - C 21 DFFE 1 3 0 2 |LEDRUN:40|d_ff18~102 (|LEDRUN:40|:65)
- 6 - C 21 DFFE 1 2 0 3 |LEDRUN:40|d_ff17~102 (|LEDRUN:40|:66)
- 3 - C 35 DFFE 1 3 0 2 |LEDRUN:40|d_ff16~102 (|LEDRUN:40|:67)
- 1 - C 35 DFFE 1 2 0 3 |LEDRUN:40|d_ff15~102 (|LEDRUN:40|:68)
- 7 - C 20 DFFE 1 3 0 2 |LEDRUN:40|d_ff14~102 (|LEDRUN:40|:69)
- 4 - C 20 DFFE 1 3 0 3 |LEDRUN:40|d_ff13~102 (|LEDRUN:40|:70)
- 3 - C 20 DFFE 1 2 0 4 |LEDRUN:40|d_ff12~102 (|LEDRUN:40|:71)
- 1 - C 20 DFFE 1 2 0 2 |LEDRUN:40|d_ff11~102 (|LEDRUN:40|:72)
- 1 - C 25 DFFE 1 3 0 3 |LEDRUN:40|d_ff10~102 (|LEDRUN:40|:73)
- 8 - C 25 DFFE 1 2 0 4 |LEDRUN:40|d_ff9~102 (|LEDRUN:40|:74)
- 6 - C 25 DFFE 1 3 0 2 |LEDRUN:40|d_ff8~102 (|LEDRUN:40|:75)
- 4 - C 25 DFFE 1 2 0 3 |LEDRUN:40|d_ff7~102 (|LEDRUN:40|:76)
- 5 - C 30 DFFE 1 3 0 1 |LEDRUN:40|d_ff6~102 (|LEDRUN:40|:77)
- 3 - C 30 DFFE 1 3 0 2 |LEDRUN:40|d_ff5~102 (|LEDRUN:40|:78)
- 1 - C 30 DFFE 1 2 0 3 |LEDRUN:40|d_ff4~102 (|LEDRUN:40|:79)
- 8 - C 35 DFFE 1 3 0 1 |LEDRUN:40|d_ff3~102 (|LEDRUN:40|:80)
- 6 - C 35 DFFE 1 3 0 2 |LEDRUN:40|d_ff2~102 (|LEDRUN:40|:81)
- 4 - C 35 DFFE 1 2 0 3 |LEDRUN:40|d_ff1~102 (|LEDRUN:40|:82)
- 5 - C 35 DFFE 1 1 0 4 |LEDRUN:40|d_ff0~102 (|LEDRUN:40|:83)
- 1 - C 21 OR2 s 0 3 0 1 |LEDRUN:40|~107~1
- 2 - C 21 OR2 0 4 0 21 |LEDRUN:40|:107
- 8 - C 20 OR2 0 4 0 1 |LEDRUN:40|:132
- 2 - C 20 AND2 s 0 4 0 1 |LEDRUN:40|~134~1
- 3 - C 25 AND2 0 3 0 1 |LEDRUN:40|:159
- 2 - B 18 AND2 s 0 4 0 1 |LEDRUN:40|~781~1
- 3 - B 18 AND2 s 0 4 0 1 |LEDRUN:40|~781~2
- 8 - B 14 AND2 s 0 3 0 1 |LEDRUN:40|~781~3
- 4 - B 14 AND2 s 0 4 0 1 |LEDRUN:40|~781~4
- 4 - B 18 AND2 s 0 4 0 1 |LEDRUN:40|~781~5
- 8 - B 18 AND2 0 4 0 1 |LEDRUN:40|:781
- 5 - B 18 OR2 s 0 4 0 1 |LEDRUN:40|~838~1
- 4 - B 12 OR2 s 0 3 0 1 |LEDRUN:40|~838~2
- 6 - B 18 OR2 s 0 4 0 1 |LEDRUN:40|~838~3
- 6 - B 14 OR2 s 0 4 0 1 |LEDRUN:40|~838~4
- 7 - B 18 OR2 s 0 4 0 1 |LEDRUN:40|~838~5
- 1 - B 18 OR2 ! 0 4 0 18 |LEDRUN:40|:838
- 5 - E 15 DFFE 1 1 0 1 |STATE:14|mode (|STATE:14|:4)
- 1 - E 08 OR2 0 2 0 9 |TIME:17|LPM_ADD_SUB:462|addcore:adder|pcarry1
- 2 - E 13 OR2 0 3 0 1 |TIME:17|LPM_ADD_SUB:462|addcore:adder|:77
- 8 - E 06 DFFE ! 1 3 0 6 |TIME:17|tim15 (|TIME:17|:12)
- 6 - E 06 DFFE 1 3 0 7 |TIME:17|tim14 (|TIME:17|:13)
- 3 - E 06 DFFE 1 5 0 9 |TIME:17|tim13 (|TIME:17|:14)
- 3 - E 13 DFFE ! 1 3 0 9 |TIME:17|tim12 (|TIME:17|:15)
- 2 - E 06 DFFE 1 3 0 14 |TIME:17|tim11 (|TIME:17|:16)
- 1 - E 06 DFFE 1 4 0 13 |TIME:17|tim10 (|TIME:17|:17)
- 4 - E 06 AND2 0 3 1 17 |TIME:17|:51
- 8 - E 15 OR2 0 3 0 6 |TIME:17|:192
- 8 - E 13 OR2 ! 0 3 0 8 |TIME:17|:257
- 6 - E 08 OR2 ! 0 3 0 2 |XDELED:21|:55
- 4 - E 11 OR2 s 0 3 0 3 |XDELED:21|~67~1
- 3 - E 23 AND2 0 2 0 1 |XDELED:21|:67
- 1 - E 09 OR2 0 3 0 2 |XDELED:21|:96
- 7 - E 11 AND2 s ! 0 3 0 4 |XDELED:21|~103~1
- 7 - E 08 AND2 s ! 0 2 0 5 |XDELED:21|~103~2
- 4 - E 13 AND2 0 4 0 2 |XDELED:21|:115
- 5 - E 08 AND2 s 0 2 0 3 |XDELED:21|~151~1
- 5 - E 13 OR2 s 0 4 0 2 |XDELED:21|~154~1
- 4 - E 09 OR2 s 0 4 0 1 |XDELED:21|~154~2
- 6 - E 11 AND2 s 0 3 0 7 |XDELED:21|~163~1
- 3 - E 09 OR2 ! 0 2 0 2 |XDELED:21|:163
- 5 - E 11 OR2 s 0 3 0 2 |XDELED:21|~175~1
- 8 - E 11 AND2 0 3 0 3 |XDELED:21|:175
- 6 - E 09 OR2 0 4 0 1 |XDELED:21|:180
- 3 - E 11 AND2 0 3 0 4 |XDELED:21|:187
- 3 - E 08 OR2 s 0 2 0 4 |XDELED:21|~190~1
- 2 - E 11 OR2 s 0 4 0 6 |XDELED:21|~211~1
- 6 - E 15 OR2 0 4 1 0 |XDELED:21|:214
- 3 - E 14 OR2 0 4 0 2 |XDELED:21|:241
- 6 - E 14 OR2 s 0 2 0 1 |XDELED:21|~262~1
- 8 - E 14 OR2 0 4 1 0 |XDELED:21|:262
- 4 - E 08 OR2 s 0 3 0 4 |XDELED:21|~301~1
- 2 - E 09 OR2 s 0 3 0 1 |XDELED:21|~301~2
- 7 - E 14 OR2 0 4 1 0 |XDELED:21|:310
- 1 - E 11 AND2 s 0 4 0 1 |XDELED:21|~358~1
- 8 - E 23 OR2 s 0 4 0 1 |XDELED:21|~358~2
- 6 - E 13 OR2 s 0 4 0 1 |XDELED:21|~358~3
- 7 - E 13 OR2 s 0 4 0 1 |XDELED:21|~358~4
- 1 - E 13 OR2 s 0 4 0 1 |XDELED:21|~358~5
- 5 - E 14 OR2 0 4 1 0 |XDELED:21|:358
- 2 - E 08 OR2 0 3 0 1 |XDELED:21|:400
- 8 - E 08 OR2 s 0 4 0 1 |XDELED:21|~402~1
- 5 - E 12 OR2 0 3 1 0 |XDELED:21|:406
- 2 - E 14 OR2 ! 0 3 0 2 |XDELED:21|:438
- 1 - E 14 OR2 0 4 0 1 |XDELED:21|:442
- 8 - E 12 OR2 0 4 1 0 |XDELED:21|:454
- 8 - E 09 OR2 0 4 0 1 |XDELED:21|:486
- 7 - E 09 OR2 s 0 4 0 2 |XDELED:21|~496~1
- 4 - E 14 AND2 s ! 0 1 0 2 |XDELED:21|~504~1
- 5 - E 09 OR2 0 4 1 0 |XDELED:21|:504
- 3 - E 05 AND2 0 2 0 3 |XIAODOU:5|LPM_ADD_SUB:92|addcore:adder|:63
- 1 - E 05 DFFE ! 1 2 0 1 |XIAODOU:5|:3
- 8 - E 05 DFFE 1 4 0 1 |XIAODOU:5|counter4 (|XIAODOU:5|:5)
- 7 - E 05 DFFE 1 4 0 2 |XIAODOU:5|counter3 (|XIAODOU:5|:6)
- 6 - E 05 DFFE 1 4 0 3 |XIAODOU:5|counter2 (|XIAODOU:5|:7)
- 5 - E 05 DFFE 1 3 0 2 |XIAODOU:5|counter1 (|XIAODOU:5|:8)
- 2 - E 05 DFFE 1 1 0 3 |XIAODOU:5|counter0 (|XIAODOU:5|:9)
- 4 - E 05 OR2 ! 0 4 0 4 |XIAODOU:5|:53
- 3 - E 02 AND2 0 2 0 3 |XIAODOU:6|LPM_ADD_SUB:92|addcore:adder|:63
- 1 - E 02 DFFE ! 1 2 0 1 |XIAODOU:6|:3
- 8 - E 02 DFFE 1 4 0 1 |XIAODOU:6|counter4 (|XIAODOU:6|:5)
- 7 - E 02 DFFE 1 4 0 2 |XIAODOU:6|counter3 (|XIAODOU:6|:6)
- 6 - E 02 DFFE 1 4 0 3 |XIAODOU:6|counter2 (|XIAODOU:6|:7)
- 5 - E 02 DFFE 1 3 0 2 |XIAODOU:6|counter1 (|XIAODOU:6|:8)
- 2 - E 02 DFFE 1 1 0 3 |XIAODOU:6|counter0 (|XIAODOU:6|:9)
- 4 - E 02 OR2 ! 0 4 0 4 |XIAODOU:6|:53
- 1 - E 23 DFFE + 1 0 0 4 |XSET:19|sel1 (|XSET:19|:14)
- 3 - E 15 OR2 ! 0 3 0 2 |XSET:19|:246
- 2 - E 23 AND2 1 1 1 7 |XSET:19|:266
- 5 - E 06 OR2 1 3 0 5 |XSET:19|:284
- 4 - E 15 OR2 ! 1 3 0 4 |XSET:19|:290
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: h:\24miao\24second.rpt
24second
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
B: 15/144( 10%) 11/ 72( 15%) 0/ 72( 0%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
C: 24/144( 16%) 2/ 72( 2%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
D: 0/144( 0%) 1/ 72( 1%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
E: 25/144( 17%) 26/ 72( 36%) 0/ 72( 0%) 3/16( 18%) 3/16( 18%) 0/16( 0%)
F: 0/144( 0%) 3/ 72( 4%) 0/ 72( 0%) 4/16( 25%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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