📄 24second.rpt
字号:
RESERVED | 26 131 | RESERVED
RESERVED | 27 EP1K30QC208-3 130 | VCCINT
RESERVED | 28 129 | GND
RESERVED | 29 128 | q13
RESERVED | 30 127 | RESERVED
RESERVED | 31 126 | RESERVED
GND | 32 125 | RESERVED
VCCINT | 33 124 | VCCINT
VCCIO | 34 123 | GND
GND | 35 122 | q17
RESERVED | 36 121 | q18
RESERVED | 37 120 | RESERVED
alert | 38 119 | RESERVED
sw1 | 39 118 | VCCIO
sw2 | 40 117 | GND
sw3 | 41 116 | RESERVED
VCCIO | 42 115 | q22
GND | 43 114 | q23
sw4 | 44 113 | RESERVED
sw5 | 45 112 | RESERVED
sw6 | 46 111 | q26
sw7 | 47 110 | VCCIO
VCCINT | 48 109 | GND
GND | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
s R R R R R G R R R R R R V R s R R r V s s R G V G c G G G R V R a b c d e V f g R R R R V R R R R R R
w E E E E E N E E E E E E C E e E E e C t e E N C N k N N N E C E C E E E E C E E E E E E
8 S S S S S D S S S S S S C S l S S s C a t S D C D d D D D S C S C S S S S C S S S S S S
E E E E E E E E E E E I E E E e I _ t E I s E I E I E E E E I E E E E E E
R R R R R R R R R R R O R R R t N p i R N p R O R N R R R R O R R R R R R
V V V V V V V V V V V V V V T u m V T V V T V V V V V V V V V V
E E E E E E E E E E E E E E l e E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: h:\24miao\24second.rpt
24second
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
B3 6/ 8( 75%) 6/ 8( 75%) 6/ 8( 75%) 2/2 0/2 8/22( 36%)
B12 8/ 8(100%) 2/ 8( 25%) 8/ 8(100%) 1/2 0/2 6/22( 27%)
B14 8/ 8(100%) 4/ 8( 50%) 6/ 8( 75%) 1/2 0/2 7/22( 31%)
B18 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 17/22( 77%)
C6 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 3/22( 13%)
C7 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 2/22( 9%)
C14 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
C20 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
C21 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 5/22( 22%)
C25 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 4/22( 18%)
C29 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 1/22( 4%)
C30 5/ 8( 62%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 3/22( 13%)
C33 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 4/22( 18%)
C35 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 3/22( 13%)
E2 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
E5 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
E6 8/ 8(100%) 2/ 8( 25%) 6/ 8( 75%) 2/2 1/2 7/22( 31%)
E8 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 8/22( 36%)
E9 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 12/22( 54%)
E11 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 6/22( 27%)
E12 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 5/22( 22%)
E13 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 11/22( 50%)
E14 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 15/22( 68%)
E15 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 2/2 1/2 12/22( 54%)
E18 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
E23 4/ 8( 50%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 6/22( 27%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 2/6 ( 33%)
Total I/O pins used: 39/141 ( 27%)
Total logic cells used: 181/1728 ( 10%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.20/4 ( 80%)
Total fan-in: 581/6912 ( 8%)
Total input pins required: 14
Total input I/O cell registers required: 0
Total output pins required: 27
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 181
Total flipflops required: 83
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 38/1728 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 6 0 0 0 0 0 0 0 0 8 0 8 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30/0
C: 0 0 0 0 0 3 2 0 0 0 0 0 0 8 0 0 0 0 0 0 8 8 0 0 0 8 0 0 0 8 5 0 0 7 0 8 0 65/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 8 0 0 8 8 0 8 8 0 8 2 8 8 8 0 0 8 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 86/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 8 6 0 8 11 2 8 8 0 8 10 8 24 8 0 0 16 0 0 8 8 0 4 0 8 0 0 0 8 5 0 0 7 0 8 0 181/0
Device-Specific Information: h:\24miao\24second.rpt
24second
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
79 - - - -- INPUT G ^ 0 0 0 0 ckdsp
150 - - A -- INPUT ^ 0 0 0 22 ckkk
183 - - - -- INPUT G ^ 0 0 0 0 clock
71 - - - 21 INPUT ^ 0 0 0 11 reset
74 - - - 20 INPUT ^ 0 0 0 6 settime
73 - - - 20 INPUT ^ 0 0 0 6 sta_pul
39 - - E -- INPUT ^ 0 0 0 0 sw1
40 - - E -- INPUT ^ 0 0 0 0 sw2
41 - - E -- INPUT ^ 0 0 0 0 sw3
44 - - F -- INPUT ^ 0 0 0 0 sw4
45 - - F -- INPUT ^ 0 0 0 0 sw5
46 - - F -- INPUT ^ 0 0 0 0 sw6
47 - - F -- INPUT ^ 0 0 0 0 sw7
53 - - - 36 INPUT ^ 0 0 0 0 sw8
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: h:\24miao\24second.rpt
24second
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
86 - - - 15 OUTPUT 0 1 0 0 a
38 - - E -- OUTPUT 0 1 0 0 alert
87 - - - 14 OUTPUT 0 1 0 0 b
88 - - - 14 OUTPUT 0 1 0 0 c
89 - - - 13 OUTPUT 0 1 0 0 d
90 - - - 12 OUTPUT 0 1 0 0 e
92 - - - 11 OUTPUT 0 1 0 0 f
93 - - - 10 OUTPUT 0 1 0 0 g
134 - - C -- OUTPUT 0 1 0 0 q9
142 - - B -- OUTPUT 0 1 0 0 q10
143 - - B -- OUTPUT 0 1 0 0 q11
144 - - B -- OUTPUT 0 1 0 0 q12
128 - - D -- OUTPUT 0 1 0 0 q13
141 - - B -- OUTPUT 0 1 0 0 q14
140 - - B -- OUTPUT 0 1 0 0 q15
139 - - B -- OUTPUT 0 1 0 0 q16
122 - - E -- OUTPUT 0 1 0 0 q17
121 - - E -- OUTPUT 0 1 0 0 q18
170 - - - 11 OUTPUT 0 1 0 0 q19
172 - - - 12 OUTPUT 0 1 0 0 q20
173 - - - 13 OUTPUT 0 1 0 0 q21
115 - - F -- OUTPUT 0 1 0 0 q22
114 - - F -- OUTPUT 0 1 0 0 q23
160 - - - 04 OUTPUT 0 1 0 0 q24
161 - - - 04 OUTPUT 0 1 0 0 q25
111 - - F -- OUTPUT 0 1 0 0 q26
68 - - - 24 OUTPUT 0 1 0 0 sel
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -