xiaodou.vhd

来自「24秒倒计时系统（有跑马灯） 利用CPLD」· VHDL 代码 · 共 32 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY xiaodou IS
PORT(
	CLOCK:IN STD_LOGIC;
	SIN:IN STD_LOGIC;
	SOUT:OUT STD_LOGIC
	);
END xiaodou;

ARCHITECTURE xd_arc OF xiaodou IS
SIGNAL counter:INTEGER RANGE 0 TO 19;
BEGIN
PROCESS(CLOCK)
BEGIN
IF SIN='1' THEN
	counter<=0;
	SOUT<='1';
ELSE
	IF RISING_EDGE(CLOCK) THEN
	IF counter=19 THEN
		counter<=0;
		SOUT<='0';
	ELSE
		counter<=counter+1;
	END IF;
	END IF;
END IF;
END PROCESS;
END xd_arc;