ivga.fit.qmsg

用VHDL写的计算器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 11 13:23:43 2006 " "Info: Processing started: Thu May 11 13:23:43 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off Ivga -c Ivga " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off Ivga -c Ivga" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "Ivga EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"Ivga\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk_vga Global clock in PIN 152 " "Info: Automatically promoted signal \"clk_vga\" to use Global clock in PIN 152" {  } { { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "VgaInterface:u2\|clk Global clock " "Info: Automatically promoted some destinations of signal \"VgaInterface:u2\|clk\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "VgaInterface:u2\|clk " "Info: Destination \"VgaInterface:u2\|clk\" may be non-global or may not use global clock" {  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 23 -1 0 } }  } 0}  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 23 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "reset Global clock " "Info: Automatically promoted some destinations of signal \"reset\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cal:u1\|vb\[0\]~339 " "Info: Destination \"cal:u1\|vb\[0\]~339\" may be non-global or may not use global clock" {  } { { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 18 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cal:u1\|va\[0\]~275 " "Info: Destination \"cal:u1\|va\[0\]~275\" may be non-global or may not use global clock" {  } { { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 18 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cal:u1\|opin~177 " "Info: Destination \"cal:u1\|opin~177\" may be non-global or may not use global clock" {  } { { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 19 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cal:u1\|op\[0\]~208 " "Info: Destination \"cal:u1\|op\[0\]~208\" may be non-global or may not use global clock" {  } { { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 20 -1 0 } }  } 0}  } { { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 6 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "reset " "Info: Pin \"reset\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "reset" } } } } { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "" { reset } "NODE_NAME" } "" } } { "E:/altera/quartus50/Ivga/Ivga.fld" "" { Floorplan "E:/altera/quartus50/Ivga/Ivga.fld" "" "" { reset } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "7.879 ns register register " "Info: Estimated most critical path is register to register delay of 7.879 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VgaInterface:u2\|vector_y\[3\] 1 REG LAB_X8_Y14 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X8_Y14; Fanout = 6; REG Node = 'VgaInterface:u2\|vector_y\[3\]'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "" { VgaInterface:u2|vector_y[3] } "NODE_NAME" } "" } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 34 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(0.590 ns) 0.740 ns VgaInterface:u2\|process4~713 2 COMB LAB_X8_Y14 1 " "Info: 2: + IC(0.150 ns) + CELL(0.590 ns) = 0.740 ns; Loc. = LAB_X8_Y14; Fanout = 1; COMB Node = 'VgaInterface:u2\|process4~713'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "0.740 ns" { VgaInterface:u2|vector_y[3] VgaInterface:u2|process4~713 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.776 ns) + CELL(0.114 ns) 1.630 ns VgaInterface:u2\|process4~714 3 COMB LAB_X9_Y14 1 " "Info: 3: + IC(0.776 ns) + CELL(0.114 ns) = 1.630 ns; Loc. = LAB_X9_Y14; Fanout = 1; COMB Node = 'VgaInterface:u2\|process4~714'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "0.890 ns" { VgaInterface:u2|process4~713 VgaInterface:u2|process4~714 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.372 ns) + CELL(0.292 ns) 2.294 ns VgaInterface:u2\|process4~715 4 COMB LAB_X9_Y14 6 " "Info: 4: + IC(0.372 ns) + CELL(0.292 ns) = 2.294 ns; Loc. = LAB_X9_Y14; Fanout = 6; COMB Node = 'VgaInterface:u2\|process4~715'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "0.664 ns" { VgaInterface:u2|process4~714 VgaInterface:u2|process4~715 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.257 ns) + CELL(0.114 ns) 3.665 ns VgaInterface:u2\|process4~720 5 COMB LAB_X9_Y13 1 " "Info: 5: + IC(1.257 ns) + CELL(0.114 ns) = 3.665 ns; Loc. = LAB_X9_Y13; Fanout = 1; COMB Node = 'VgaInterface:u2\|process4~720'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "1.371 ns" { VgaInterface:u2|process4~715 VgaInterface:u2|process4~720 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.442 ns) 5.036 ns VgaInterface:u2\|char_address\[13\]~647 6 COMB LAB_X9_Y14 11 " "Info: 6: + IC(0.929 ns) + CELL(0.442 ns) = 5.036 ns; Loc. = LAB_X9_Y14; Fanout = 11; COMB Node = 'VgaInterface:u2\|char_address\[13\]~647'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "1.371 ns" { VgaInterface:u2|process4~720 VgaInterface:u2|char_address[13]~647 } "NODE_NAME" } "" } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.074 ns) + CELL(0.590 ns) 5.700 ns VgaInterface:u2\|char_address\[13\]~661 7 COMB LAB_X9_Y14 4 " "Info: 7: + IC(0.074 ns) + CELL(0.590 ns) = 5.700 ns; Loc. = LAB_X9_Y14; Fanout = 4; COMB Node = 'VgaInterface:u2\|char_address\[13\]~661'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "0.664 ns" { VgaInterface:u2|char_address[13]~647 VgaInterface:u2|char_address[13]~661 } "NODE_NAME" } "" } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.067 ns) + CELL(1.112 ns) 7.879 ns VgaInterface:u2\|char_address\[12\] 8 REG LAB_X6_Y14 1 " "Info: 8: + IC(1.067 ns) + CELL(1.112 ns) = 7.879 ns; Loc. = LAB_X6_Y14; Fanout = 1; REG Node = 'VgaInterface:u2\|char_address\[12\]'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "2.179 ns" { VgaInterface:u2|char_address[13]~661 VgaInterface:u2|char_address[12] } "NODE_NAME" } "" } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.254 ns 41.30 % " "Info: Total cell delay = 3.254 ns ( 41.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.625 ns 58.70 % " "Info: Total interconnect delay = 4.625 ns ( 58.70 % )" {  } {  } 0}  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "7.879 ns" { VgaInterface:u2|vector_y[3] VgaInterface:u2|process4~713 VgaInterface:u2|process4~714 VgaInterface:u2|process4~715 VgaInterface:u2|process4~720 VgaInterface:u2|char_address[13]~647 VgaInterface:u2|char_address[13]~661 VgaInterface:u2|char_address[12] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 3 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 3%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 11 13:23:48 2006 " "Info: Processing ended: Thu May 11 13:23:48 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}