ivga.tan.qmsg

用VHDL写的计算器

{ "Info" "ITDB_TSU_RESULT" "cal:u1\|vb\[0\] DATA\[2\] clk_vga 9.363 ns register " "Info: tsu for register \"cal:u1\|vb\[0\]\" (data pin = \"DATA\[2\]\", clock pin = \"clk_vga\") is 9.363 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.280 ns + Longest pin register " "Info: + Longest pin to register delay is 12.280 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns DATA\[2\] 1 PIN PIN_235 6 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_235; Fanout = 6; PIN Node = 'DATA\[2\]'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "" { DATA[2] } "NODE_NAME" } "" } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.167 ns) + CELL(0.590 ns) 7.232 ns cal:u1\|COMREG~178 2 COMB LC_X5_Y17_N8 7 " "Info: 2: + IC(5.167 ns) + CELL(0.590 ns) = 7.232 ns; Loc. = LC_X5_Y17_N8; Fanout = 7; COMB Node = 'cal:u1\|COMREG~178'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "5.757 ns" { DATA[2] cal:u1|COMREG~178 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.261 ns) + CELL(0.442 ns) 8.935 ns cal:u1\|vb\[0\]~338 3 COMB LC_X5_Y16_N5 1 " "Info: 3: + IC(1.261 ns) + CELL(0.442 ns) = 8.935 ns; Loc. = LC_X5_Y16_N5; Fanout = 1; COMB Node = 'cal:u1\|vb\[0\]~338'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "1.703 ns" { cal:u1|COMREG~178 cal:u1|vb[0]~338 } "NODE_NAME" } "" } } { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.442 ns) + CELL(0.442 ns) 9.819 ns cal:u1\|vb\[0\]~339 4 COMB LC_X5_Y16_N4 4 " "Info: 4: + IC(0.442 ns) + CELL(0.442 ns) = 9.819 ns; Loc. = LC_X5_Y16_N4; Fanout = 4; COMB Node = 'cal:u1\|vb\[0\]~339'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "0.884 ns" { cal:u1|vb[0]~338 cal:u1|vb[0]~339 } "NODE_NAME" } "" } } { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.594 ns) + CELL(0.867 ns) 12.280 ns cal:u1\|vb\[0\] 5 REG LC_X6_Y15_N7 10 " "Info: 5: + IC(1.594 ns) + CELL(0.867 ns) = 12.280 ns; Loc. = LC_X6_Y15_N7; Fanout = 10; REG Node = 'cal:u1\|vb\[0\]'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "2.461 ns" { cal:u1|vb[0]~339 cal:u1|vb[0] } "NODE_NAME" } "" } } { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.816 ns 31.07 % " "Info: Total cell delay = 3.816 ns ( 31.07 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.464 ns 68.93 % " "Info: Total interconnect delay = 8.464 ns ( 68.93 % )" {  } {  } 0}  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "12.280 ns" { DATA[2] cal:u1|COMREG~178 cal:u1|vb[0]~338 cal:u1|vb[0]~339 cal:u1|vb[0] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "12.280 ns" { DATA[2] DATA[2]~out0 cal:u1|COMREG~178 cal:u1|vb[0]~338 cal:u1|vb[0]~339 cal:u1|vb[0] } { 0.000ns 0.000ns 5.167ns 1.261ns 0.442ns 1.594ns } { 0.000ns 1.475ns 0.590ns 0.442ns 0.442ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_vga destination 2.954 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_vga\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_vga 1 CLK PIN_152 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 19; CLK Node = 'clk_vga'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "" { clk_vga } "NODE_NAME" } "" } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns cal:u1\|vb\[0\] 2 REG LC_X6_Y15_N7 10 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X6_Y15_N7; Fanout = 10; REG Node = 'cal:u1\|vb\[0\]'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "1.485 ns" { clk_vga cal:u1|vb[0] } "NODE_NAME" } "" } } { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "2.954 ns" { clk_vga cal:u1|vb[0] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk_vga clk_vga~out0 cal:u1|vb[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "12.280 ns" { DATA[2] cal:u1|COMREG~178 cal:u1|vb[0]~338 cal:u1|vb[0]~339 cal:u1|vb[0] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "12.280 ns" { DATA[2] DATA[2]~out0 cal:u1|COMREG~178 cal:u1|vb[0]~338 cal:u1|vb[0]~339 cal:u1|vb[0] } { 0.000ns 0.000ns 5.167ns 1.261ns 0.442ns 1.594ns } { 0.000ns 1.475ns 0.590ns 0.442ns 0.442ns 0.867ns } } } { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "2.954 ns" { clk_vga cal:u1|vb[0] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk_vga clk_vga~out0 cal:u1|vb[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_vga Ovga_g VgaInterface:u2\|pod_vga_r 12.234 ns register " "Info: tco from clock \"clk_vga\" to destination pin \"Ovga_g\" through register \"VgaInterface:u2\|pod_vga_r\" is 12.234 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_vga source 7.399 ns + Longest register " "Info: + Longest clock path from clock \"clk_vga\" to source register is 7.399 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_vga 1 CLK PIN_152 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 19; CLK Node = 'clk_vga'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "" { clk_vga } "NODE_NAME" } "" } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns VgaInterface:u2\|clk 2 REG LC_X8_Y10_N2 117 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N2; Fanout = 117; REG Node = 'VgaInterface:u2\|clk'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "1.680 ns" { clk_vga VgaInterface:u2|clk } "NODE_NAME" } "" } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.539 ns) + CELL(0.711 ns) 7.399 ns VgaInterface:u2\|pod_vga_r 3 REG LC_X11_Y14_N8 3 " "Info: 3: + IC(3.539 ns) + CELL(0.711 ns) = 7.399 ns; Loc. = LC_X11_Y14_N8; Fanout = 3; REG Node = 'VgaInterface:u2\|pod_vga_r'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "4.250 ns" { VgaInterface:u2|clk VgaInterface:u2|pod_vga_r } "NODE_NAME" } "" } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 42.10 % " "Info: Total cell delay = 3.115 ns ( 42.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.284 ns 57.90 % " "Info: Total interconnect delay = 4.284 ns ( 57.90 % )" {  } {  } 0}  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "7.399 ns" { clk_vga VgaInterface:u2|clk VgaInterface:u2|pod_vga_r } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.399 ns" { clk_vga clk_vga~out0 VgaInterface:u2|clk VgaInterface:u2|pod_vga_r } { 0.000ns 0.000ns 0.745ns 3.539ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.611 ns + Longest register pin " "Info: + Longest register to pin delay is 4.611 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VgaInterface:u2\|pod_vga_r 1 REG LC_X11_Y14_N8 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y14_N8; Fanout = 3; REG Node = 'VgaInterface:u2\|pod_vga_r'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "" { VgaInterface:u2|pod_vga_r } "NODE_NAME" } "" } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.503 ns) + CELL(2.108 ns) 4.611 ns Ovga_g 2 PIN PIN_225 0 " "Info: 2: + IC(2.503 ns) + CELL(2.108 ns) = 4.611 ns; Loc. = PIN_225; Fanout = 0; PIN Node = 'Ovga_g'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "4.611 ns" { VgaInterface:u2|pod_vga_r Ovga_g } "NODE_NAME" } "" } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 45.72 % " "Info: Total cell delay = 2.108 ns ( 45.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.503 ns 54.28 % " "Info: Total interconnect delay = 2.503 ns ( 54.28 % )" {  } {  } 0}  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "4.611 ns" { VgaInterface:u2|pod_vga_r Ovga_g } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "4.611 ns" { VgaInterface:u2|pod_vga_r Ovga_g } { 0.000ns 2.503ns } { 0.000ns 2.108ns } } }  } 0}  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "7.399 ns" { clk_vga VgaInterface:u2|clk VgaInterface:u2|pod_vga_r } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.399 ns" { clk_vga clk_vga~out0 VgaInterface:u2|clk VgaInterface:u2|pod_vga_r } { 0.000ns 0.000ns 0.745ns 3.539ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "4.611 ns" { VgaInterface:u2|pod_vga_r Ovga_g } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "4.611 ns" { VgaInterface:u2|pod_vga_r Ovga_g } { 0.000ns 2.503ns } { 0.000ns 2.108ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "cal:u1\|va\[3\] DATA\[3\] clk_vga -4.267 ns register " "Info: th for register \"cal:u1\|va\[3\]\" (data pin = \"DATA\[3\]\", clock pin = \"clk_vga\") is -4.267 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_vga destination 2.954 ns + Longest register " "Info: + Longest clock path from clock \"clk_vga\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_vga 1 CLK PIN_152 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 19; CLK Node = 'clk_vga'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "" { clk_vga } "NODE_NAME" } "" } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns cal:u1\|va\[3\] 2 REG LC_X6_Y17_N5 5 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X6_Y17_N5; Fanout = 5; REG Node = 'cal:u1\|va\[3\]'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "1.485 ns" { clk_vga cal:u1|va[3] } "NODE_NAME" } "" } } { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "2.954 ns" { clk_vga cal:u1|va[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk_vga clk_vga~out0 cal:u1|va[3] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.236 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.236 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns DATA\[3\] 1 PIN PIN_236 6 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_236; Fanout = 6; PIN Node = 'DATA\[3\]'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "" { DATA[3] } "NODE_NAME" } "" } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.452 ns) + CELL(0.309 ns) 7.236 ns cal:u1\|va\[3\] 2 REG LC_X6_Y17_N5 5 " "Info: 2: + IC(5.452 ns) + CELL(0.309 ns) = 7.236 ns; Loc. = LC_X6_Y17_N5; Fanout = 5; REG Node = 'cal:u1\|va\[3\]'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "5.761 ns" { DATA[3] cal:u1|va[3] } "NODE_NAME" } "" } } { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.784 ns 24.65 % " "Info: Total cell delay = 1.784 ns ( 24.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.452 ns 75.35 % " "Info: Total interconnect delay = 5.452 ns ( 75.35 % )" {  } {  } 0}  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "7.236 ns" { DATA[3] cal:u1|va[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.236 ns" { DATA[3] DATA[3]~out0 cal:u1|va[3] } { 0.000ns 0.000ns 5.452ns } { 0.000ns 1.475ns 0.309ns } } }  } 0}  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "2.954 ns" { clk_vga cal:u1|va[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk_vga clk_vga~out0 cal:u1|va[3] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "7.236 ns" { DATA[3] cal:u1|va[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.236 ns" { DATA[3] DATA[3]~out0 cal:u1|va[3] } { 0.000ns 0.000ns 5.452ns } { 0.000ns 1.475ns 0.309ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 11 13:23:54 2006 " "Info: Processing ended: Thu May 11 13:23:54 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}