ivga.tan.qmsg

用VHDL写的计算器

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "VgaInterface:u2\|clk " "Info: Detected ripple clock \"VgaInterface:u2\|clk\" as buffer" {  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 23 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "VgaInterface:u2\|clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_vga register VgaInterface:u2\|vector_x\[6\] register VgaInterface:u2\|char_address\[10\] 101.6 MHz 9.843 ns Internal " "Info: Clock \"clk_vga\" has Internal fmax of 101.6 MHz between source register \"VgaInterface:u2\|vector_x\[6\]\" and destination register \"VgaInterface:u2\|char_address\[10\]\" (period= 9.843 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.582 ns + Longest register register " "Info: + Longest register to register delay is 9.582 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VgaInterface:u2\|vector_x\[6\] 1 REG LC_X9_Y13_N8 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y13_N8; Fanout = 9; REG Node = 'VgaInterface:u2\|vector_x\[6\]'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "" { VgaInterface:u2|vector_x[6] } "NODE_NAME" } "" } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.442 ns) 1.002 ns VgaInterface:u2\|process4~711 2 COMB LC_X9_Y13_N5 3 " "Info: 2: + IC(0.560 ns) + CELL(0.442 ns) = 1.002 ns; Loc. = LC_X9_Y13_N5; Fanout = 3; COMB Node = 'VgaInterface:u2\|process4~711'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "1.002 ns" { VgaInterface:u2|vector_x[6] VgaInterface:u2|process4~711 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.112 ns) + CELL(0.292 ns) 2.406 ns VgaInterface:u2\|process4~718 3 COMB LC_X9_Y13_N0 2 " "Info: 3: + IC(1.112 ns) + CELL(0.292 ns) = 2.406 ns; Loc. = LC_X9_Y13_N0; Fanout = 2; COMB Node = 'VgaInterface:u2\|process4~718'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "1.404 ns" { VgaInterface:u2|process4~711 VgaInterface:u2|process4~718 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.557 ns) + CELL(0.590 ns) 4.553 ns VgaInterface:u2\|char_address\[13\]~646 4 COMB LC_X9_Y14_N6 8 " "Info: 4: + IC(1.557 ns) + CELL(0.590 ns) = 4.553 ns; Loc. = LC_X9_Y14_N6; Fanout = 8; COMB Node = 'VgaInterface:u2\|char_address\[13\]~646'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "2.147 ns" { VgaInterface:u2|process4~718 VgaInterface:u2|char_address[13]~646 } "NODE_NAME" } "" } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.445 ns) + CELL(0.114 ns) 5.112 ns VgaInterface:u2\|char_address\[13\]~658 5 COMB LC_X9_Y14_N3 7 " "Info: 5: + IC(0.445 ns) + CELL(0.114 ns) = 5.112 ns; Loc. = LC_X9_Y14_N3; Fanout = 7; COMB Node = 'VgaInterface:u2\|char_address\[13\]~658'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "0.559 ns" { VgaInterface:u2|char_address[13]~646 VgaInterface:u2|char_address[13]~658 } "NODE_NAME" } "" } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.158 ns) + CELL(0.590 ns) 6.860 ns VgaInterface:u2\|char_address~659 6 COMB LC_X7_Y14_N6 1 " "Info: 6: + IC(1.158 ns) + CELL(0.590 ns) = 6.860 ns; Loc. = LC_X7_Y14_N6; Fanout = 1; COMB Node = 'VgaInterface:u2\|char_address~659'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "1.748 ns" { VgaInterface:u2|char_address[13]~658 VgaInterface:u2|char_address~659 } "NODE_NAME" } "" } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.432 ns) + CELL(0.590 ns) 7.882 ns VgaInterface:u2\|char_address~660 7 COMB LC_X7_Y14_N7 1 " "Info: 7: + IC(0.432 ns) + CELL(0.590 ns) = 7.882 ns; Loc. = LC_X7_Y14_N7; Fanout = 1; COMB Node = 'VgaInterface:u2\|char_address~660'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "1.022 ns" { VgaInterface:u2|char_address~659 VgaInterface:u2|char_address~660 } "NODE_NAME" } "" } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.093 ns) + CELL(0.607 ns) 9.582 ns VgaInterface:u2\|char_address\[10\] 8 REG LC_X9_Y14_N4 4 " "Info: 8: + IC(1.093 ns) + CELL(0.607 ns) = 9.582 ns; Loc. = LC_X9_Y14_N4; Fanout = 4; REG Node = 'VgaInterface:u2\|char_address\[10\]'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "1.700 ns" { VgaInterface:u2|char_address~660 VgaInterface:u2|char_address[10] } "NODE_NAME" } "" } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.225 ns 33.66 % " "Info: Total cell delay = 3.225 ns ( 33.66 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.357 ns 66.34 % " "Info: Total interconnect delay = 6.357 ns ( 66.34 % )" {  } {  } 0}  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "9.582 ns" { VgaInterface:u2|vector_x[6] VgaInterface:u2|process4~711 VgaInterface:u2|process4~718 VgaInterface:u2|char_address[13]~646 VgaInterface:u2|char_address[13]~658 VgaInterface:u2|char_address~659 VgaInterface:u2|char_address~660 VgaInterface:u2|char_address[10] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "9.582 ns" { VgaInterface:u2|vector_x[6] VgaInterface:u2|process4~711 VgaInterface:u2|process4~718 VgaInterface:u2|char_address[13]~646 VgaInterface:u2|char_address[13]~658 VgaInterface:u2|char_address~659 VgaInterface:u2|char_address~660 VgaInterface:u2|char_address[10] } { 0.000ns 0.560ns 1.112ns 1.557ns 0.445ns 1.158ns 0.432ns 1.093ns } { 0.000ns 0.442ns 0.292ns 0.590ns 0.114ns 0.590ns 0.590ns 0.607ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_vga destination 7.399 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_vga\" to destination register is 7.399 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_vga 1 CLK PIN_152 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 19; CLK Node = 'clk_vga'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "" { clk_vga } "NODE_NAME" } "" } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns VgaInterface:u2\|clk 2 REG LC_X8_Y10_N2 117 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N2; Fanout = 117; REG Node = 'VgaInterface:u2\|clk'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "1.680 ns" { clk_vga VgaInterface:u2|clk } "NODE_NAME" } "" } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.539 ns) + CELL(0.711 ns) 7.399 ns VgaInterface:u2\|char_address\[10\] 3 REG LC_X9_Y14_N4 4 " "Info: 3: + IC(3.539 ns) + CELL(0.711 ns) = 7.399 ns; Loc. = LC_X9_Y14_N4; Fanout = 4; REG Node = 'VgaInterface:u2\|char_address\[10\]'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "4.250 ns" { VgaInterface:u2|clk VgaInterface:u2|char_address[10] } "NODE_NAME" } "" } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 42.10 % " "Info: Total cell delay = 3.115 ns ( 42.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.284 ns 57.90 % " "Info: Total interconnect delay = 4.284 ns ( 57.90 % )" {  } {  } 0}  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "7.399 ns" { clk_vga VgaInterface:u2|clk VgaInterface:u2|char_address[10] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.399 ns" { clk_vga clk_vga~out0 VgaInterface:u2|clk VgaInterface:u2|char_address[10] } { 0.000ns 0.000ns 0.745ns 3.539ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_vga source 7.399 ns - Longest register " "Info: - Longest clock path from clock \"clk_vga\" to source register is 7.399 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_vga 1 CLK PIN_152 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 19; CLK Node = 'clk_vga'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "" { clk_vga } "NODE_NAME" } "" } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns VgaInterface:u2\|clk 2 REG LC_X8_Y10_N2 117 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N2; Fanout = 117; REG Node = 'VgaInterface:u2\|clk'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "1.680 ns" { clk_vga VgaInterface:u2|clk } "NODE_NAME" } "" } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.539 ns) + CELL(0.711 ns) 7.399 ns VgaInterface:u2\|vector_x\[6\] 3 REG LC_X9_Y13_N8 9 " "Info: 3: + IC(3.539 ns) + CELL(0.711 ns) = 7.399 ns; Loc. = LC_X9_Y13_N8; Fanout = 9; REG Node = 'VgaInterface:u2\|vector_x\[6\]'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "4.250 ns" { VgaInterface:u2|clk VgaInterface:u2|vector_x[6] } "NODE_NAME" } "" } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 42.10 % " "Info: Total cell delay = 3.115 ns ( 42.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.284 ns 57.90 % " "Info: Total interconnect delay = 4.284 ns ( 57.90 % )" {  } {  } 0}  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "7.399 ns" { clk_vga VgaInterface:u2|clk VgaInterface:u2|vector_x[6] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.399 ns" { clk_vga clk_vga~out0 VgaInterface:u2|clk VgaInterface:u2|vector_x[6] } { 0.000ns 0.000ns 0.745ns 3.539ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "7.399 ns" { clk_vga VgaInterface:u2|clk VgaInterface:u2|char_address[10] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.399 ns" { clk_vga clk_vga~out0 VgaInterface:u2|clk VgaInterface:u2|char_address[10] } { 0.000ns 0.000ns 0.745ns 3.539ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "7.399 ns" { clk_vga VgaInterface:u2|clk VgaInterface:u2|vector_x[6] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.399 ns" { clk_vga clk_vga~out0 VgaInterface:u2|clk VgaInterface:u2|vector_x[6] } { 0.000ns 0.000ns 0.745ns 3.539ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 36 -1 0 } }  } 0}  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "9.582 ns" { VgaInterface:u2|vector_x[6] VgaInterface:u2|process4~711 VgaInterface:u2|process4~718 VgaInterface:u2|char_address[13]~646 VgaInterface:u2|char_address[13]~658 VgaInterface:u2|char_address~659 VgaInterface:u2|char_address~660 VgaInterface:u2|char_address[10] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "9.582 ns" { VgaInterface:u2|vector_x[6] VgaInterface:u2|process4~711 VgaInterface:u2|process4~718 VgaInterface:u2|char_address[13]~646 VgaInterface:u2|char_address[13]~658 VgaInterface:u2|char_address~659 VgaInterface:u2|char_address~660 VgaInterface:u2|char_address[10] } { 0.000ns 0.560ns 1.112ns 1.557ns 0.445ns 1.158ns 0.432ns 1.093ns } { 0.000ns 0.442ns 0.292ns 0.590ns 0.114ns 0.590ns 0.590ns 0.607ns } } } { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "7.399 ns" { clk_vga VgaInterface:u2|clk VgaInterface:u2|char_address[10] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.399 ns" { clk_vga clk_vga~out0 VgaInterface:u2|clk VgaInterface:u2|char_address[10] } { 0.000ns 0.000ns 0.745ns 3.539ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "7.399 ns" { clk_vga VgaInterface:u2|clk VgaInterface:u2|vector_x[6] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.399 ns" { clk_vga clk_vga~out0 VgaInterface:u2|clk VgaInterface:u2|vector_x[6] } { 0.000ns 0.000ns 0.745ns 3.539ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk_vga 80 " "Warning: Circuit may not operate. Detected 80 non-operational path(s) clocked by clock \"clk_vga\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "cal:u1\|op\[2\] VgaInterface:u2\|vga_data\[18\] clk_vga 3.215 ns " "Info: Found hold time violation between source  pin or register \"cal:u1\|op\[2\]\" and destination pin or register \"VgaInterface:u2\|vga_data\[18\]\" for clock \"clk_vga\" (Hold time is 3.215 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.445 ns + Largest " "Info: + Largest clock skew is 4.445 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_vga destination 7.399 ns + Longest register " "Info: + Longest clock path from clock \"clk_vga\" to destination register is 7.399 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_vga 1 CLK PIN_152 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 19; CLK Node = 'clk_vga'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "" { clk_vga } "NODE_NAME" } "" } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns VgaInterface:u2\|clk 2 REG LC_X8_Y10_N2 117 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N2; Fanout = 117; REG Node = 'VgaInterface:u2\|clk'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "1.680 ns" { clk_vga VgaInterface:u2|clk } "NODE_NAME" } "" } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.539 ns) + CELL(0.711 ns) 7.399 ns VgaInterface:u2\|vga_data\[18\] 3 REG LC_X6_Y16_N6 1 " "Info: 3: + IC(3.539 ns) + CELL(0.711 ns) = 7.399 ns; Loc. = LC_X6_Y16_N6; Fanout = 1; REG Node = 'VgaInterface:u2\|vga_data\[18\]'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "4.250 ns" { VgaInterface:u2|clk VgaInterface:u2|vga_data[18] } "NODE_NAME" } "" } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 42.10 % " "Info: Total cell delay = 3.115 ns ( 42.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.284 ns 57.90 % " "Info: Total interconnect delay = 4.284 ns ( 57.90 % )" {  } {  } 0}  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "7.399 ns" { clk_vga VgaInterface:u2|clk VgaInterface:u2|vga_data[18] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.399 ns" { clk_vga clk_vga~out0 VgaInterface:u2|clk VgaInterface:u2|vga_data[18] } { 0.0ns 0.0ns 0.745ns 3.539ns } { 0.0ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_vga source 2.954 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_vga\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_vga 1 CLK PIN_152 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 19; CLK Node = 'clk_vga'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "" { clk_vga } "NODE_NAME" } "" } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns cal:u1\|op\[2\] 2 REG LC_X6_Y16_N4 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X6_Y16_N4; Fanout = 1; REG Node = 'cal:u1\|op\[2\]'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "1.485 ns" { clk_vga cal:u1|op[2] } "NODE_NAME" } "" } } { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "2.954 ns" { clk_vga cal:u1|op[2] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk_vga clk_vga~out0 cal:u1|op[2] } { 0.0ns 0.0ns 0.774ns } { 0.0ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "7.399 ns" { clk_vga VgaInterface:u2|clk VgaInterface:u2|vga_data[18] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.399 ns" { clk_vga clk_vga~out0 VgaInterface:u2|clk VgaInterface:u2|vga_data[18] } { 0.0ns 0.0ns 0.745ns 3.539ns } { 0.0ns 1.469ns 0.935ns 0.711ns } } } { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "2.954 ns" { clk_vga cal:u1|op[2] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk_vga clk_vga~out0 cal:u1|op[2] } { 0.0ns 0.0ns 0.774ns } { 0.0ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.021 ns - Shortest register register " "Info: - Shortest register to register delay is 1.021 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cal:u1\|op\[2\] 1 REG LC_X6_Y16_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y16_N4; Fanout = 1; REG Node = 'cal:u1\|op\[2\]'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "" { cal:u1|op[2] } "NODE_NAME" } "" } } { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.543 ns) + CELL(0.478 ns) 1.021 ns VgaInterface:u2\|vga_data\[18\] 2 REG LC_X6_Y16_N6 1 " "Info: 2: + IC(0.543 ns) + CELL(0.478 ns) = 1.021 ns; Loc. = LC_X6_Y16_N6; Fanout = 1; REG Node = 'VgaInterface:u2\|vga_data\[18\]'" {  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "1.021 ns" { cal:u1|op[2] VgaInterface:u2|vga_data[18] } "NODE_NAME" } "" } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns 46.82 % " "Info: Total cell delay = 0.478 ns ( 46.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.543 ns 53.18 % " "Info: Total interconnect delay = 0.543 ns ( 53.18 % )" {  } {  } 0}  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "1.021 ns" { cal:u1|op[2] VgaInterface:u2|vga_data[18] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "1.021 ns" { cal:u1|op[2] VgaInterface:u2|vga_data[18] } { 0.0ns 0.543ns } { 0.0ns 0.478ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 22 -1 0 } }  } 0}  } { { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "7.399 ns" { clk_vga VgaInterface:u2|clk VgaInterface:u2|vga_data[18] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.399 ns" { clk_vga clk_vga~out0 VgaInterface:u2|clk VgaInterface:u2|vga_data[18] } { 0.0ns 0.0ns 0.745ns 3.539ns } { 0.0ns 1.469ns 0.935ns 0.711ns } } } { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "2.954 ns" { clk_vga cal:u1|op[2] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk_vga clk_vga~out0 cal:u1|op[2] } { 0.0ns 0.0ns 0.774ns } { 0.0ns 1.469ns 0.711ns } } } { "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" "" { Report "E:/altera/quartus50/Ivga/db/Ivga_cmp.qrpt" Compiler "Ivga" "UNKNOWN" "V1" "E:/altera/quartus50/Ivga/db/Ivga.quartus_db" { Floorplan "E:/altera/quartus50/Ivga/" "" "1.021 ns" { cal:u1|op[2] VgaInterface:u2|vga_data[18] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "1.021 ns" { cal:u1|op[2] VgaInterface:u2|vga_data[18] } { 0.0ns 0.543ns } { 0.0ns 0.478ns } } }  } 0}