ivga.map.qmsg

用VHDL写的计算器

{ "Info" "ISGN_SEARCH_FILE" "vga.vhd 2 1 " "Info: Using design file vga.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 vga-SYN " "Info: Found design unit 1: vga-SYN" {  } { { "vga.vhd" "" { Text "E:/altera/quartus50/Ivga/vga.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 vga " "Info: Found entity 1: vga" {  } { { "vga.vhd" "" { Text "E:/altera/quartus50/Ivga/vga.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga VgaInterface:u2\|vga:u1 " "Info: Elaborating entity \"vga\" for hierarchy \"VgaInterface:u2\|vga:u1\"" {  } { { "vgainterface.vhd" "u1" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 47 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\"" {  } { { "vga.vhd" "altsyncram_component" { Text "E:/altera/quartus50/Ivga/vga.vhd" 80 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_7mv.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_7mv.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_7mv " "Info: Found entity 1: altsyncram_7mv" {  } { { "db/altsyncram_7mv.tdf" "" { Text "E:/altera/quartus50/Ivga/db/altsyncram_7mv.tdf" 36 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_7mv VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated " "Info: Elaborating entity \"altsyncram_7mv\" for hierarchy \"VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_gcb.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_gcb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_gcb " "Info: Found entity 1: mux_gcb" {  } { { "db/mux_gcb.tdf" "" { Text "E:/altera/quartus50/Ivga/db/mux_gcb.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_gcb VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|mux_gcb:mux2 " "Info: Elaborating entity \"mux_gcb\" for hierarchy \"VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|mux_gcb:mux2\"" {  } { { "db/altsyncram_7mv.tdf" "mux2" { Text "E:/altera/quartus50/Ivga/db/altsyncram_7mv.tdf" 44 2 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "VgaInterface:u2\|char_address\[15\] data_in GND " "Warning: Reduced register \"VgaInterface:u2\|char_address\[15\]\" with stuck data_in port to stuck value GND" {  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 36 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "VgaInterface:u2\|char_address\[14\] data_in GND " "Warning: Reduced register \"VgaInterface:u2\|char_address\[14\]\" with stuck data_in port to stuck value GND" {  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 36 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|address_reg_a\[3\] data_in GND " "Warning: Reduced register \"VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|address_reg_a\[3\]\" with stuck data_in port to stuck value GND" {  } { { "db/altsyncram_7mv.tdf" "" { Text "E:/altera/quartus50/Ivga/db/altsyncram_7mv.tdf" 43 15 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|address_reg_a\[2\] data_in GND " "Warning: Reduced register \"VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|address_reg_a\[2\]\" with stuck data_in port to stuck value GND" {  } { { "db/altsyncram_7mv.tdf" "" { Text "E:/altera/quartus50/Ivga/db/altsyncram_7mv.tdf" 43 15 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|address_reg_a\[7\] data_in GND " "Warning: Reduced register \"VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|address_reg_a\[7\]\" with stuck data_in port to stuck value GND" {  } { { "db/altsyncram_7mv.tdf" "" { Text "E:/altera/quartus50/Ivga/db/altsyncram_7mv.tdf" 43 15 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|address_reg_a\[6\] data_in GND " "Warning: Reduced register \"VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|address_reg_a\[6\]\" with stuck data_in port to stuck value GND" {  } { { "db/altsyncram_7mv.tdf" "" { Text "E:/altera/quartus50/Ivga/db/altsyncram_7mv.tdf" 43 15 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Warning: Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Warning: Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a4 " "Warning: Synthesized away node \"VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a4\"" {  } { { "db/altsyncram_7mv.tdf" "" { Text "E:/altera/quartus50/Ivga/db/altsyncram_7mv.tdf" 121 2 0 } } { "altsyncram.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } } { "vga.vhd" "" { Text "E:/altera/quartus50/Ivga/vga.vhd" 80 -1 0 } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 47 -1 0 } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 39 -1 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a5 " "Warning: Synthesized away node \"VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a5\"" {  } { { "db/altsyncram_7mv.tdf" "" { Text "E:/altera/quartus50/Ivga/db/altsyncram_7mv.tdf" 140 2 0 } } { "altsyncram.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } } { "vga.vhd" "" { Text "E:/altera/quartus50/Ivga/vga.vhd" 80 -1 0 } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 47 -1 0 } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 39 -1 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a6 " "Warning: Synthesized away node \"VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a6\"" {  } { { "db/altsyncram_7mv.tdf" "" { Text "E:/altera/quartus50/Ivga/db/altsyncram_7mv.tdf" 159 2 0 } } { "altsyncram.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } } { "vga.vhd" "" { Text "E:/altera/quartus50/Ivga/vga.vhd" 80 -1 0 } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 47 -1 0 } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 39 -1 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a7 " "Warning: Synthesized away node \"VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a7\"" {  } { { "db/altsyncram_7mv.tdf" "" { Text "E:/altera/quartus50/Ivga/db/altsyncram_7mv.tdf" 178 2 0 } } { "altsyncram.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } } { "vga.vhd" "" { Text "E:/altera/quartus50/Ivga/vga.vhd" 80 -1 0 } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 47 -1 0 } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 39 -1 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a8 " "Warning: Synthesized away node \"VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a8\"" {  } { { "db/altsyncram_7mv.tdf" "" { Text "E:/altera/quartus50/Ivga/db/altsyncram_7mv.tdf" 197 2 0 } } { "altsyncram.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } } { "vga.vhd" "" { Text "E:/altera/quartus50/Ivga/vga.vhd" 80 -1 0 } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 47 -1 0 } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 39 -1 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a9 " "Warning: Synthesized away node \"VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a9\"" {  } { { "db/altsyncram_7mv.tdf" "" { Text "E:/altera/quartus50/Ivga/db/altsyncram_7mv.tdf" 216 2 0 } } { "altsyncram.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } } { "vga.vhd" "" { Text "E:/altera/quartus50/Ivga/vga.vhd" 80 -1 0 } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 47 -1 0 } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 39 -1 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a10 " "Warning: Synthesized away node \"VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a10\"" {  } { { "db/altsyncram_7mv.tdf" "" { Text "E:/altera/quartus50/Ivga/db/altsyncram_7mv.tdf" 235 2 0 } } { "altsyncram.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } } { "vga.vhd" "" { Text "E:/altera/quartus50/Ivga/vga.vhd" 80 -1 0 } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 47 -1 0 } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 39 -1 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a11 " "Warning: Synthesized away node \"VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a11\"" {  } { { "db/altsyncram_7mv.tdf" "" { Text "E:/altera/quartus50/Ivga/db/altsyncram_7mv.tdf" 254 2 0 } } { "altsyncram.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } } { "vga.vhd" "" { Text "E:/altera/quartus50/Ivga/vga.vhd" 80 -1 0 } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 47 -1 0 } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 39 -1 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a12 " "Warning: Synthesized away node \"VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a12\"" {  } { { "db/altsyncram_7mv.tdf" "" { Text "E:/altera/quartus50/Ivga/db/altsyncram_7mv.tdf" 273 2 0 } } { "altsyncram.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } } { "vga.vhd" "" { Text "E:/altera/quartus50/Ivga/vga.vhd" 80 -1 0 } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 47 -1 0 } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 39 -1 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a13 " "Warning: Synthesized away node \"VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a13\"" {  } { { "db/altsyncram_7mv.tdf" "" { Text "E:/altera/quartus50/Ivga/db/altsyncram_7mv.tdf" 292 2 0 } } { "altsyncram.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } } { "vga.vhd" "" { Text "E:/altera/quartus50/Ivga/vga.vhd" 80 -1 0 } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 47 -1 0 } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 39 -1 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a14 " "Warning: Synthesized away node \"VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a14\"" {  } { { "db/altsyncram_7mv.tdf" "" { Text "E:/altera/quartus50/Ivga/db/altsyncram_7mv.tdf" 311 2 0 } } { "altsyncram.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } } { "vga.vhd" "" { Text "E:/altera/quartus50/Ivga/vga.vhd" 80 -1 0 } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 47 -1 0 } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 39 -1 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a15 " "Warning: Synthesized away node \"VgaInterface:u2\|vga:u1\|altsyncram:altsyncram_component\|altsyncram_7mv:auto_generated\|ram_block1a15\"" {  } { { "db/altsyncram_7mv.tdf" "" { Text "E:/altera/quartus50/Ivga/db/altsyncram_7mv.tdf" 330 2 0 } } { "altsyncram.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } } { "vga.vhd" "" { Text "E:/altera/quartus50/Ivga/vga.vhd" 80 -1 0 } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 47 -1 0 } } { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 39 -1 0 } }  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "VgaInterface:u2\|vga_data\[10\] VgaInterface:u2\|vga_data\[11\] " "Info: Duplicate register \"VgaInterface:u2\|vga_data\[10\]\" merged to single register \"VgaInterface:u2\|vga_data\[11\]\"" {  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 22 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "VgaInterface:u2\|vga_data\[8\] VgaInterface:u2\|vga_data\[9\] " "Info: Duplicate register \"VgaInterface:u2\|vga_data\[8\]\" merged to single register \"VgaInterface:u2\|vga_data\[9\]\"" {  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 22 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "VgaInterface:u2\|vga_g VgaInterface:u2\|vga_r " "Info: Duplicate register \"VgaInterface:u2\|vga_g\" merged to single register \"VgaInterface:u2\|vga_r\"" {  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 25 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "VgaInterface:u2\|vga_b VgaInterface:u2\|vga_r " "Info: Duplicate register \"VgaInterface:u2\|vga_b\" merged to single register \"VgaInterface:u2\|vga_r\"" {  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 26 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "VgaInterface:u2\|vga_data\[6\] VgaInterface:u2\|vga_data\[7\] " "Info: Duplicate register \"VgaInterface:u2\|vga_data\[6\]\" merged to single register \"VgaInterface:u2\|vga_data\[7\]\"" {  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 22 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "VgaInterface:u2\|vga_data\[5\] VgaInterface:u2\|vga_data\[7\] " "Info: Duplicate register \"VgaInterface:u2\|vga_data\[5\]\" merged to single register \"VgaInterface:u2\|vga_data\[7\]\"" {  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 22 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "VgaInterface:u2\|pod_vga_g VgaInterface:u2\|pod_vga_r " "Info: Duplicate register \"VgaInterface:u2\|pod_vga_g\" merged to single register \"VgaInterface:u2\|pod_vga_r\"" {  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "VgaInterface:u2\|pod_vga_b VgaInterface:u2\|pod_vga_r " "Info: Duplicate register \"VgaInterface:u2\|pod_vga_b\" merged to single register \"VgaInterface:u2\|pod_vga_r\"" {  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 15 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|Ivga\|cal:u1\|STX 5 0 " "Info: State machine \"\|Ivga\|cal:u1\|STX\" contains 5 states and 0 state bits" {  } { { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 17 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|Ivga\|cal:u1\|STX " "Info: Selected Auto state machine encoding method for state machine \"\|Ivga\|cal:u1\|STX\"" {  } { { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 17 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|Ivga\|cal:u1\|STX " "Info: Encoding result for state machine \"\|Ivga\|cal:u1\|STX\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cal:u1\|STX.st4 " "Info: Encoded state bit \"cal:u1\|STX.st4\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cal:u1\|STX.st3 " "Info: Encoded state bit \"cal:u1\|STX.st3\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cal:u1\|STX.st2 " "Info: Encoded state bit \"cal:u1\|STX.st2\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cal:u1\|STX.st1 " "Info: Encoded state bit \"cal:u1\|STX.st1\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cal:u1\|STX.st0 " "Info: Encoded state bit \"cal:u1\|STX.st0\"" {  } {  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Ivga\|cal:u1\|STX.st0 00000 " "Info: State \"\|Ivga\|cal:u1\|STX.st0\" uses code string \"00000\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Ivga\|cal:u1\|STX.st1 00011 " "Info: State \"\|Ivga\|cal:u1\|STX.st1\" uses code string \"00011\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Ivga\|cal:u1\|STX.st2 00101 " "Info: State \"\|Ivga\|cal:u1\|STX.st2\" uses code string \"00101\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Ivga\|cal:u1\|STX.st3 01001 " "Info: State \"\|Ivga\|cal:u1\|STX.st3\" uses code string \"01001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Ivga\|cal:u1\|STX.st4 10001 " "Info: State \"\|Ivga\|cal:u1\|STX.st4\" uses code string \"10001\"" {  } {  } 0}  } { { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 17 -1 0 } }  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 29 -1 0 } } { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 30 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "186 " "Info: Implemented 186 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "170 " "Info: Implemented 170 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "4 " "Info: Implemented 4 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 20 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 20 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 11 13:23:40 2006 " "Info: Processing ended: Thu May 11 13:23:40 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}