ivga.map.qmsg

用VHDL写的计算器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 11 13:23:35 2006 " "Info: Processing started: Thu May 11 13:23:35 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Ivga -c Ivga " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Ivga -c Ivga" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Ivga.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Ivga.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Ivga-beh " "Info: Found design unit 1: Ivga-beh" {  } { { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 Ivga " "Info: Found entity 1: Ivga" {  } { { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vgainterface.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file vgainterface.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 VgaInterface-behavior " "Info: Found design unit 1: VgaInterface-behavior" {  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 21 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 VgaInterface " "Info: Found entity 1: VgaInterface" {  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cal.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cal.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cal-behav " "Info: Found design unit 1: cal-behav" {  } { { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 cal " "Info: Found entity 1: cal" {  } { { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bcd.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file bcd.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bcd-Impl " "Info: Found design unit 1: bcd-Impl" {  } { { "bcd.vhd" "" { Text "E:/altera/quartus50/Ivga/bcd.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 bcd " "Info: Found entity 1: bcd" {  } { { "bcd.vhd" "" { Text "E:/altera/quartus50/Ivga/bcd.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bcd4adder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file bcd4adder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 BCD4Adder-Impl " "Info: Found design unit 1: BCD4Adder-Impl" {  } { { "bcd4adder.vhd" "" { Text "E:/altera/quartus50/Ivga/bcd4adder.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 BCD4Adder " "Info: Found entity 1: BCD4Adder" {  } { { "bcd4adder.vhd" "" { Text "E:/altera/quartus50/Ivga/bcd4adder.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BCD4suber.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file BCD4suber.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 BCD4suber-Impl " "Info: Found design unit 1: BCD4suber-Impl" {  } { { "BCD4suber.vhd" "" { Text "E:/altera/quartus50/Ivga/BCD4suber.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 BCD4suber " "Info: Found entity 1: BCD4suber" {  } { { "BCD4suber.vhd" "" { Text "E:/altera/quartus50/Ivga/BCD4suber.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Complementor.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Complementor.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Complementor-Impl " "Info: Found design unit 1: Complementor-Impl" {  } { { "Complementor.vhd" "" { Text "E:/altera/quartus50/Ivga/Complementor.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 Complementor " "Info: Found entity 1: Complementor" {  } { { "Complementor.vhd" "" { Text "E:/altera/quartus50/Ivga/Complementor.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "F4a_adder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file F4a_adder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 F4a_adder-Impl " "Info: Found design unit 1: F4a_adder-Impl" {  } { { "F4a_adder.vhd" "" { Text "E:/altera/quartus50/Ivga/F4a_adder.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 F4a_adder " "Info: Found entity 1: F4a_adder" {  } { { "F4a_adder.vhd" "" { Text "E:/altera/quartus50/Ivga/F4a_adder.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f_adder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file f_adder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 f_adder-fd " "Info: Found design unit 1: f_adder-fd" {  } { { "f_adder.vhd" "" { Text "E:/altera/quartus50/Ivga/f_adder.vhd" 7 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 f_adder " "Info: Found entity 1: f_adder" {  } { { "f_adder.vhd" "" { Text "E:/altera/quartus50/Ivga/f_adder.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Ivga " "Info: Elaborating entity \"Ivga\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cal cal:u1 " "Info: Elaborating entity \"cal\" for hierarchy \"cal:u1\"" {  } { { "Ivga.vhd" "u1" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 38 -1 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "cal.vhd(67) " "Info: VHDL Case Statement information at cal.vhd(67): OTHERS choice is never selected" {  } { { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 67 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "cal.vhd(95) " "Info: VHDL Case Statement information at cal.vhd(95): OTHERS choice is never selected" {  } { { "cal.vhd" "" { Text "E:/altera/quartus50/Ivga/cal.vhd" 95 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bcd cal:u1\|bcd:u1 " "Info: Elaborating entity \"bcd\" for hierarchy \"cal:u1\|bcd:u1\"" {  } { { "cal.vhd" "u1" { Text "E:/altera/quartus50/Ivga/cal.vhd" 71 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BCD4Adder cal:u1\|bcd:u1\|BCD4Adder:ua " "Info: Elaborating entity \"BCD4Adder\" for hierarchy \"cal:u1\|bcd:u1\|BCD4Adder:ua\"" {  } { { "bcd.vhd" "ua" { Text "E:/altera/quartus50/Ivga/bcd.vhd" 28 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "F4a_adder cal:u1\|bcd:u1\|BCD4Adder:ua\|F4a_adder:u1 " "Info: Elaborating entity \"F4a_adder\" for hierarchy \"cal:u1\|bcd:u1\|BCD4Adder:ua\|F4a_adder:u1\"" {  } { { "bcd4adder.vhd" "u1" { Text "E:/altera/quartus50/Ivga/bcd4adder.vhd" 24 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "f_adder cal:u1\|bcd:u1\|BCD4Adder:ua\|F4a_adder:u1\|f_adder:u1 " "Info: Elaborating entity \"f_adder\" for hierarchy \"cal:u1\|bcd:u1\|BCD4Adder:ua\|F4a_adder:u1\|f_adder:u1\"" {  } { { "F4a_adder.vhd" "u1" { Text "E:/altera/quartus50/Ivga/F4a_adder.vhd" 17 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BCD4suber cal:u1\|bcd:u1\|BCD4suber:us " "Info: Elaborating entity \"BCD4suber\" for hierarchy \"cal:u1\|bcd:u1\|BCD4suber:us\"" {  } { { "bcd.vhd" "us" { Text "E:/altera/quartus50/Ivga/bcd.vhd" 30 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Complementor cal:u1\|bcd:u1\|BCD4suber:us\|Complementor:u1 " "Info: Elaborating entity \"Complementor\" for hierarchy \"cal:u1\|bcd:u1\|BCD4suber:us\|Complementor:u1\"" {  } { { "BCD4suber.vhd" "u1" { Text "E:/altera/quartus50/Ivga/BCD4suber.vhd" 27 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "VgaInterface VgaInterface:u2 " "Info: Elaborating entity \"VgaInterface\" for hierarchy \"VgaInterface:u2\"" {  } { { "Ivga.vhd" "u2" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 39 -1 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "vga_hs vgainterface.vhd(27) " "Info: (10035) Verilog HDL or VHDL information at vgainterface.vhd(27): object \"vga_hs\" declared but not used" {  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 27 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "vga_vs vgainterface.vhd(28) " "Info: (10035) Verilog HDL or VHDL information at vgainterface.vhd(28): object \"vga_vs\" declared but not used" {  } { { "vgainterface.vhd" "" { Text "E:/altera/quartus50/Ivga/vgainterface.vhd" 28 0 0 } }  } 0}