class.ptf

user_logic_VGA_Controller

CLASS user_logic_VGA_Controller
{
   ASSOCIATED_FILES 
   {
      Add_Program = "";
      Edit_Program = "";
      Generator_Program = "mk_user_logic_VGA_Controller.pl";
   }
   MODULE_DEFAULTS 
   {
      class = "user_logic_VGA_Controller";
      class_version = "2.0";
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Date_Modified = "--unknown--";
         Clock_Source = "clk";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
      }
      SLAVE avalonS
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Alignment = "native";
            Address_Width = "19";
            Data_Width = "16";
            Has_IRQ = "0";
            Has_Base_Address = "1";
            Read_Wait_States = "20ns";
            Write_Wait_States = "20ns";
            Setup_Time = "20ns";
            Hold_Time = "20ns";
            Is_Memory_Device = "0";
            Uses_Tri_State_Data_Bus = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT iDATA
            {
               width = "16";
               direction = "input";
               type = "writedata";
            }
            PORT oDATA
            {
               width = "16";
               direction = "output";
               type = "readdata";
            }
            PORT iADDR
            {
               width = "19";
               direction = "input";
               type = "address";
            }
            PORT iWR
            {
               width = "1";
               direction = "input";
               type = "write";
            }
            PORT iRD
            {
               width = "1";
               direction = "input";
               type = "read";
            }
            PORT iCS
            {
               width = "1";
               direction = "input";
               type = "chipselect";
            }
            PORT iRST_N
            {
               width = "1";
               direction = "input";
               type = "reset_n";
            }
            PORT iCLK
            {
               width = "1";
               direction = "input";
               type = "clk";
            }
            PORT VGA_R
            {
               width = "10";
               direction = "output";
               type = "export";
            }
            PORT VGA_G
            {
               width = "10";
               direction = "output";
               type = "export";
            }
            PORT VGA_B
            {
               width = "10";
               direction = "output";
               type = "export";
            }
            PORT VGA_HS
            {
               width = "1";
               direction = "output";
               type = "export";
            }
            PORT VGA_VS
            {
               width = "1";
               direction = "output";
               type = "export";
            }
            PORT VGA_SYNC
            {
               width = "1";
               direction = "output";
               type = "export";
            }
            PORT VGA_BLANK
            {
               width = "1";
               direction = "output";
               type = "export";
            }
            PORT VGA_CLK
            {
               width = "1";
               direction = "output";
               type = "export";
            }
            PORT iCLK_27
            {
               width = "1";
               direction = "input";
               type = "export";
            }
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL a
            {
               name = "iDATA";
               radix = "hexadecimal";
            }
            SIGNAL b
            {
               name = "oDATA";
               radix = "hexadecimal";
            }
            SIGNAL c
            {
               name = "iADDR";
               radix = "hexadecimal";
            }
            SIGNAL d
            {
               name = "iWR";
            }
            SIGNAL e
            {
               name = "iRD";
            }
            SIGNAL f
            {
               name = "iCS";
            }
            SIGNAL g
            {
               name = "iRST_N";
            }
            SIGNAL h
            {
               name = "iCLK";
            }
            SIGNAL i
            {
               name = "VGA_R";
               radix = "hexadecimal";
            }
            SIGNAL j
            {
               name = "VGA_G";
               radix = "hexadecimal";
            }
            SIGNAL k
            {
               name = "VGA_B";
               radix = "hexadecimal";
            }
            SIGNAL l
            {
               name = "VGA_HS";
            }
            SIGNAL m
            {
               name = "VGA_VS";
            }
            SIGNAL n
            {
               name = "VGA_SYNC";
            }
            SIGNAL o
            {
               name = "VGA_BLANK";
            }
            SIGNAL p
            {
               name = "VGA_CLK";
            }
            SIGNAL q
            {
               name = "iCLK_27";
            }
         }
      }
   }
   USER_INTERFACE 
   {
      USER_LABELS 
      {
         name = "VGA_Controller";
         technology = "User Logic";
      }
   }
   DEFAULT_GENERATOR 
   {
      top_module_name = "VGA_NIOS_CTRL";
      black_box = "0";
      vhdl_synthesis_files = "";
      verilog_synthesis_files = "Img_RAM.v,VGA_Controller.v,VGA_NIOS_CTRL.v,VGA_OSD_RAM.v,VGA_PLL.v";
      black_box_files = "";
   }
}